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19-2861; Rev 3; 2/07
KIT ATION EVALU LE B AVAILA
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
General Description
The MAX1540A/MAX1541 dual pulse-width modulation (PWM) controllers provide the high efficiency, excellent transient response, and high DC-output accuracy necessary for stepping down high-voltage batteries to generate low-voltage chipset and RAM power supplies in notebook computers. The Maxim proprietary Quick-PWMTM controllers are free running, constant on-time with input feed forward. This configuration provides ultra-fast transient response, wide input-output (I/O) differential range, low supply current, and tight load-regulation characteristics. The controllers can accurately sense the inductor current across an external current-sense resistor in series with the output to ensure reliable overload and inductor saturation protection. Alternatively, the controllers can use the synchronous rectifier itself or lossless inductor current-sensing methods to provide overload protection with lower power dissipation. For a single step-down PWM controller with inductorsaturation protection, external-reference input voltage, and dynamically selectable output voltages, refer to the MAX1992/MAX1993 data sheet.
Features
Inductor-Saturation Protection Accurate Differential Current-Sense Inputs Dual Ultra-High-Efficiency Quick-PWMs with 100ns Load-Step Response MAX1540A 1.8V/1.2V Fixed or 0.7V to 5.5V Adjustable Output (OUT1) 2.5V/1.5V Fixed or 0.7V to 5.5V Adjustable Output (OUT2) Fixed 5V, 100mA Linear Regulator MAX1541 External Reference Input (REFIN1) Dynamically Selectable Output Voltage--0.7V to 5.5V (OUT1) 2.5V/1.8V Fixed or 0.7V to 5.5V Adjustable Output (OUT2) Optional Power-Good and Fault Blanking During Transitions Fixed 5V or Adjustable 100mA Linear Regulator 1% VOUT Accuracy over Line and Load 2V to 28V Battery Input Range 170kHz to 620kHz Selectable Switching Frequency Overvoltage/Undervoltage-Protection Option 1.7ms Digital Soft-Start Drives Large Synchronous-Rectifier FETs 2V 0.7% Reference Output Separate Power-Good Window Comparators
MAX1540A/MAX1541
Applications
Notebook Computers Core/I/O Supplies as Low as 0.7V 0.7V to 5.5V Supply Rails CPU/Chipset/GPU with Dynamic Voltage Core Supplies (MAX1541) DDR Memory Termination (MAX1541) Active Termination Buses (MAX1541)
Pin Configurations
LDOOUT LDOON BST1 V+
TOP VIEW
24
23
22
21
20
19
18
Ordering Information
DH1
17
GND
DL1
DL2
LX1
25 26 27 28 29 30 31 32
16 15 14 13
BST2 LX2 DH2
PART MAX1540AETJ MAX1540AETJ+ MAX1541ETL MAX1541ETL+
TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C
PINPACKAGE 32 Thin QFN 5mm x 5mm 32 Thin QFN 5mm x 5mm 40 Thin QFN 6mm x 6mm 40 Thin QFN 6mm x 6mm
PKG CODE T3255-4 T3255-4 T4066-5
PGOOD1 OUT1
FB1 CSN1
CSP1
PGOOD2 OUT2
FB2
MAX1540A
12 11 10 9
ON2 ON1
CSN2 CSP2
1
2
3
4
5
6
7 ILIM2
OVP/UVP
ILIM1
SKIP
LSAT
TON
T4066-5
+Denotes a lead-free package. Quick-PWM is a trademark of Maxim Integrated Products, Inc.
THIN QFN
A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES.
Pin Configurations continued at end of data sheet. 1
________________________________________________________________ Maxim Integrated Products
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
VCC
REF
8
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
ABSOLUTE MAXIMUM RATINGS
V+, LDOON to GND ...............................................-0.3V to +28V LDOOUT to GND (MAX1540A, Note 1)....................-0.3V to +6V LDOOUT to GND (MAX1541, Note 1) ....................-0.3V to +28V VDD to GND (MAX1541, Note 1) ..............................-0.3V to +6V VCC, ON_ to GND.....................................................-0.3V to +6V SKIP, PGOOD_ to GND............................................-0.3V to +6V FB_, CSP_, ILIM_ to GND.........................................-0.3V to +6V TON, OVP/UVP, LSAT to GND ...................-0.3V to (VCC + 0.3V) REF, OUT_ to GND.....................................-0.3V to (VCC + 0.3V) LDOIN to GND (MAX1541).....................................-0.3V to +28V REFIN1, GATE, OD, FBLDO to GND (MAX1541).....-0.3V to +6V FBLANK, CC1 to GND (MAX1541).............-0.3V to (VCC + 0.3V) DL_ to GND (Note 1) ..................................-0.3V to (VDD + 0.3V) CSN_ to GND ............................................................-2V to +30V DH_ to LX_..................................................-0.3V to (BST + 0.3V) LX_ to GND................................................................-2V to +30V BST_ to LX_ ..............................................................-0.3V to +6V REF Short Circuit to GND ...........................................Continuous Continuous Power Dissipation (TA = +70C) 32-Pin 5mm x 5mm Thin QFN (derated 21.3mW/C above +70C).............................................................1702mW 40-Pin 6mm x 6mm Thin QFN (derated 26.3mW/C above +70C).............................................................2105mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Note 1: For the MAX1540A, the gate-driver input supply (VDD) is internally connected to the fixed 5V linear-regulator output (LDOOUT), and the linear-regulator input supply (LDOIN) is internally connected to the battery voltage input (V+).
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER INPUT SUPPLIES (Note 1) VIN Input Voltage Range VBIAS VLDOIN MAX1540A: battery voltage, V+ > VLDOOUT MAX1541: battery voltage, V+ > VLDOOUT VCC, VDD (MAX1541) MAX1541: LDO input supply, VLDOIN > VLDOOUT FB1 and FB2 forced above the regulation point, LSAT = GND Quiescent Supply Current (VCC) ICC FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC, VLSAT > 0.5V FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC MAX1540A: FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC, VLDOON = V+ = 28V MAX1541: ON1 or ON2 = VCC, VLDOON = V+ = 28V Quiescent Supply Current (LDOIN, MAX1541 Only) Standby Supply Current (VCC) ILDOIN FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC, VLDOON = V+ = 28V ON1 = ON2 = GND, VLDOON = V+ = 28V <1 25 <1 5.5 2 4.5 4.5 0.7 28 28 5.5 28 1.5 mA 1.8 5 A V SYMBOL CONDITIONS MIN TYP MAX UNITS
Quiescent Supply Current (VDD, MAX1541 Only)
IDD
150 A 40
Quiescent Supply Current (V+)
IV+
110 5
A A
2
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Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Standby Supply Current (VDD, MAX1541 Only) SYMBOL CONDITIONS ON1 = ON2 = GND, VLDOON = V+ = 28V MAX1540A: ON1 = ON2 = GND, LDOON = V+ = 28V, VCC = 0 or 5V MAX1541: ON1 = ON2 = GND, LDOON = V+ = 28V, VCC = VDD = 0 or 5V Standby Supply Current (LDOIN, MAX1541 Only) Shutdown Supply Current (VCC) Shutdown Supply Current (VDD, MAX1541 Only) ON1 = ON2 = GND, VLDOON = V+ = 28V ON1 = ON2 = LDOON = GND ON1 = ON2 = LDOON = GND MAX1540A: ON1 = ON2 = LDOON = GND, V+ = 28V, VCC = 0 or 5V MAX1541: ON1 = ON2 = LDOON = GND, V+ = 28V, VCC = VDD = 0 or 5V Shutdown Supply Current (LDOIN, MAX1541 Only) PWM CONTROLLERS VOUT1 Preset output, V+ = 5.5V to 28V, SKIP = VCC FB1 = GND FB1 = VCC 1.782 1.188 0.693 2.475 1.485 0.693 0.693 2.475 1.782 0.693 1.80 1.20 0.70 2.50 1.50 0.70 0.70 2.50 1.80 0.70 0.1 0.25 -0.1 0.7 +0.1 5.5 1.818 1.212 0.707 2.525 1.515 0.707 0.707 2.525 1.818 0.707 % % A V V V V V LDOON = GND <1 <1 4 <1 4 <1 MIN TYP <1 MAX 5 105 A 5 100 5 5 15 A 5 10 A A A A UNITS A
Standby Supply Current (V+)
Shutdown Supply Current (V+)
MAX1540A Main Output-Voltage Accuracy (OUT1) (Note 2)
VFB1
Adjustable output, V+ = 5.5V to 28V, SKIP = VCC Preset output, V+ = 5.5V to 28V, SKIP = VCC FB2 = GND FB2 = VCC
MAX1540A Secondary OutputVoltage Accuracy (OUT2) (Note 2)
VOUT2
VFB2 VFB1
Adjustable output, V+ = 5.5V to 28V, SKIP = VCC V+ = 4.5V to 28V, SKIP = VCC Preset output, V+ = 4.5V to 28V, SKIP = VCC REFIN1 = 0.35 x REF FB2 = GND FB2 = VCC
MAX1541 Main FeedbackVoltage Accuracy (FB1)
MAX1541 Secondary OutputVoltage Accuracy (OUT2) (Note 2) Load-Regulation Error Line-Regulation Error FB_ Input Bias Current Output Adjust Range
VOUT2
VFB2
Adjustable output, V+ = 4.5V to 28V, SKIP = VCC ILOAD = 0 to 3A, SKIP = VCC VCC = 4.5V to 5.5V, V+ = 4.5V to 28V
IFB_
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3
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL MAX1540A OUT_ Input Resistance ROUT_ MAX1541 CONDITIONS FB_ = GND FB_ = VCC or adjustable FB1 = OUT1 FB2 = GND FB2 = VCC or adjustable OUT_ Discharge Mode OnResistance OUT_ Synchronous-Rectifier Discharge-Mode Turn-On Level Soft-Start Ramp Time tSS Rising edge on ON_ to full current limit TON = GND (620kHz) DH1 On-Time tON1 V+ = 15V, VOUT1 = 1.5V (Note 3) TON = REF (485kHz) TON = open (345kHz) TON = VCC (235kHz) TON = GND (460kHz) DH2 On-Time tON2 V+ = 15V, VOUT2 = 1.5V (Note 3) TON = REF (355kHz) TON = open (255kHz) TON = VCC (170kHz) On-Time Tracking Minimum Off-Time MAX1540A LDO Output-Voltage Accuracy MAX1541 LDO Output-Voltage Accuracy (Fixed VLDOOUT) tOFF(MIN) LINEAR REGULATOR (LDO) (Note 1) VLDOOUT ON1 = ON2 = GND, V+ = 6V to 28V FBLDO = ON1 = ON2 = GND, VLDOIN = 6V to 28V FBLDO = LDOOUT, ON1 = ON2 = GND, VLDOIN = 4.5V to 28V 0 < ILDOOUT < 10mA 0 < ILDOOUT < 100mA 0 < ILDOOUT < 10mA 0 < ILDOOUT < 100mA 0 < ILDOOUT < 10mA 0 < ILDOOUT < 100mA 4.85 4.70 4.85 4.70 1.212 1.175 1.175 130 IFBLDO MAX1540A: V+ - VLDOOUT, ILDOOUT = 50mA Dropout Voltage MAX1541: VLDOIN - VLDOOUT, ILDOOUT = 50mA -0.1 500 500 +0.1 800 800 mV 1.25 5.0 5.0 5.10 5.10 5.10 V 5.10 1.275 V 1.275 24 V mA A V tON2 with respect to tON1 (Note 3) (Note 3) 149 191 274 402 201 260 371 556 120 RDISCHARGE 0.2 MIN 70 50 400 90 60 TYP 145 115 700 170 130 10 0.3 1.7 169 216 304 447 228 296 412 618 135 400 190 242 335 491 256 331 453 679 150 500 % ns ns ns MAX 350 220 1500 350 270 25 0.4 V ms k UNITS
VLDOOUT
MAX1541 LDO Feedback Accuracy (Adjustable VLDOOUT) MAX1541 LDO Output Adjust Range LDOOUT Short-Circuit Current FBLDO Input Bias Current
VFBLDO
4
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Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER REFERENCE (REF) Reference Voltage Reference Load Regulation REF Lockout Voltage REFIN1 (MAX1541) Voltage Range REFIN1 (MAX1541) Input Bias Current FAULT DETECTION Overvoltage Trip Threshold Overvoltage Fault-Propagation Delay Output Undervoltage-Protection Trip Threshold Output Undervoltage-Protection Blanking Time Output Undervoltage FaultPropagation Delay PGOOD_ Lower Trip Threshold PGOOD_ Upper Trip Threshold PGOOD_ Propagation Delay PGOOD_ Output Low Voltage PGOOD_ Leakage Current Fault-Blanking Time (MAX1541 Only) Thermal-Shutdown Threshold VCC Undervoltage-Lockout Threshold CURRENT LIMIT ILIM_ Adjustment Range Current-Limit Input Range CSP_/CSN_ Input Current CSP_ CSN_ 0.25 0 -0.3 2 2.7 +28 0.5 V V A IPGOOD_ tPGOOD_ tBLANK tUVP With respect to error-comparator threshold, hysteresis = 1% With respect to error-comparator threshold, hysteresis = 1% FB forced 2% beyond PGOOD_ trip threshold ISINK = 4mA FB = REF (PGOOD high impedance), PGOOD forced to 5.5V FBLANK = VCC tFBLANK FBLANK = open FBLANK = REF TSHDN VUVLO(VCC) Hysteresis = 10C LDOON = VCC LDOON = GND 4.1 120 80 35 220 140 65 +150 +160 4.25 4.4 -13 +7 tOVP With respect to error-comparator threshold, OVP/UVP = VCC FB forced 2% above trip threshold With respect to error-comparator threshold, OVP/UVP = VCC From rising edge of ON_ 65 10 10 -10 +10 10 0.3 1 320 205 95 C V s -7 +13 12 16 10 70 75 35 20 % s % ms s % % s V A VREF VREF VCC = 4.5V to 5.5V, IREF = 0V IREF = -10A to +50A TA = +25C to +85C TA = 0C to +85C 1.986 1.983 -0.01 1.95 0.7 0.01 VREF 0.05 2.00 2.00 2.014 2.017 +0.01 V V V V A SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1540A/MAX1541
VREF(UVLO) Rising edge, hysteresis = 350mV VREFIN IREFIN1
Rising edge, PWM disabled below this level, hysteresis = 20mV
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5
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Valley Current-Limit Threshold (Fixed) Valley Current-Limit Threshold (Adjustable) Current-Limit Threshold (Negative) Current-Limit Threshold (Zero Crossing) SYMBOL CONDITIONS MIN 45 15 170 -90 TYP 50 25 200 -65 MAX 55 35 230 -45 UNITS mV mV mV
VLIM_ (VAL) VCSP_ - VCSN_, ILIM_ = VCC VLIM_ (VAL) VCSP_ - VCSN_ VNEG VILIM_ = 250mV VILIM_ = 2.00V
VCSP_ - VCSN _, SKIP = ILIM_ = VCC, TA = +25C With respect to valley current-limit threshold, VCSP_ - VCSN _, SKIP = GND, ILIM_ = VCC With respect to valley currentlimit threshold, ILIM_ = VCC LSAT = VCC LSAT = open LSAT = REF
VZX
2.5 180 157 135 4 200 175 150 6 220 193 165 8 0.1
mV
Inductor-Saturation Current-Limit Threshold ILIM_ Saturation Fault Sink Current ILIM_ Leakage Current GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance DH_ Gate-Driver Source/Sink Current DL_ Gate-Driver Source Current DL_ Gate-Driver Sink Current Dead Time INPUTS AND OUTPUTS OD On-Resistance OD Leakage Current Logic Input Threshold LDOON Input Trip Level Logic Input Current Dual ModeTM Threshold Voltage ROD RDH RDL IDH IDL (SOURCE) IDL (SINK) tDEAD
%
IILIM_ (LSAT)
VCSP - VCSN > inductor saturation current limit, 0.25V < VILIM_ < 2.0V VCSP_ - VCSN _ < inductor saturation current limit BST_-LX_ forced to 5V DL_, high state DL_, low state DH_ forced to 2.5V, BST_-LX_ forced to 5V DL_ forced to 2.5V DL_ forced to 2.5V DL_ rising DH_ rising GATE = VCC GATE = GND, OD forced to 5.5V ON1, ON2, SKIP, GATE rising edge, hysteresis = 225mV Rising edge, hysteresis = 250mV ON1, ON2, LDOON, SKIP, GATE FB1 (MAX1540A), High FB2 (MAX1540A/ Low MAX1541)
A A
1.5 1.5 0.6 1 1 3 35 26 10 1 1.2 1.20 -1 1.9 0.05 2.0 0.1 1.7 1.25
5 5 3
A A A ns
25 200 2.2 1.30 +1 2.1
nA V V A V
0.15
Dual Mode is a trademark of Maxim Integrated Products, Inc.
6
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Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS High Four-Level Input Logic Levels TON, OVP/UVP, LSAT, SKIP, FBLANK Open REF Low Four-Level Logic Input Current TON, OVP/UVP, LSAT, SKIP, FBLANK forced to GND or VCC -3 MIN VCC 0.4V 3.15 1.65 3.85 2.35 0.5 +3 A V TYP MAX UNITS
MAX1540A/MAX1541
ELECTRICAL CHARACTERISTICS
(V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = -40C to +85C, unless otherwise noted.) (Note 4)
PARAMETER INPUT SUPPLIES (Note 1) VIN Input Voltage Range VBIAS VLDOIN MAX1540A: battery voltage, V+ > VLDOOUT MAX1541: battery voltage, V+ > VLDOOUT VCC, VDD (MAX1541) MAX1541: LDO input supply, VLDOIN > VLDOOUT FB1 and FB2 forced above the regulation point, LSAT = GND Quiescent Supply Current (VCC) ICC FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC, VLSAT > 0.5V FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC MAX1540A: FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC, VLDOON = V+ = 28V MAX1541: ON1 or ON2 = VCC, VLDOON = V+ = 28V Quiescent Supply Current (LDOIN, MAX1541 Only) Standby Supply Current (VDD) Standby Supply Current (VDD, MAX1541 Only) ILDOIN FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC, VLDOON = V+ = 28V ON1 = ON2 = GND, VLDOON = V+ = 28V ON1 = ON2 = GND, VLDOON = V+ = 28V MAX1540A: ON1 = ON2 = GND, LDOON = V+ = 28V, VCC = 0 or 5V MAX1541: ON1 = ON2 = GND, LDOON = V+ = 28V, VCC = VDD = 0 or 5V Standby Supply Current (LDOIN, MAX1541 Only) ON1 = ON2 = GND, VLDOON = V+ = 28V 5.5 2 4.5 4.5 28 28 5.5 28 1.5 mA 1.8 5 A V SYMBOL CONDITIONS MIN MAX UNITS
Quiescent Supply Current (VDD, MAX1541 Only)
IDD
150 A 40
Quiescent Supply Current (V+)
IV+
110 5 5 105
A A A
Standby Supply Current (V+)
A 5 100 A
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Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = -40C to +85C, unless otherwise noted.) (Note 4)
PARAMETER Shutdown Supply Current (VCC) Shutdown Supply Current (VDD, MAX1541 Only) SYMBOL CONDITIONS ON1 = ON2 = LDOON = GND ON1 = ON2 = LDOON = GND MAX1540A: ON1 = ON2 = LDOON = GND, V+ = 28V, VCC = 0 or 5V MAX1541: ON1 = ON2 = LDOON = GND, V+ = 28V, VCC = VDD = 0 or 5V Shutdown Supply Current (LDOIN, MAX1541 Only) PWM CONTROLLERS VOUT1 Preset output, V+ = 5.5V to 28V, SKIP = VCC FB1 = GND FB1 = VCC 1.773 1.182 0.689 2.462 1.477 0.689 0.689 1.97 2.462 1.773 0.689 149 191 274 402 201 260 371 556 118 1.827 1.218 0.711 2.538 1.523 0.711 0.711 2.03 2.538 1.827 0.711 190 242 335 491 256 331 453 679 152 500 0 < ILDOOUT < 10mA 0 < ILDOOUT < 100mA 4.85 4.65 5.10 5.10 % ns ns ns V V V V LDOON = GND MIN MAX 5 5 15 A 5 10 A UNITS A A
Shutdown Supply Current (V+)
MAX1540A Main Output-Voltage Accuracy (OUT1) (Note 2)
VFB1
Adjustable output, V+ = 5.5V to 28V, SKIP = VCC Preset output, V+ = 5.5V to 28V, SKIP = VCC FB2 = GND FB2 = VCC
MAX1540A Secondary OutputVoltage Accuracy (OUT2) (Note 2) MAX1541 Main Feedback Voltage Accuracy (FB1)
VOUT2
VFB2 VFB1
Adjustable output, V+ = 5.5V to 28V, SKIP = VCC V+ = 4.5V to 28V, SKIP = VCC Preset output, V+ = 4.5V to 28V, SKIP = VCC REFIN1 = 0.35 x REF REFIN1 = REF FB2 = GND FB2 = VCC
MAX1541 Secondary OutputVoltage Accuracy (OUT2) (Note 2)
VOUT2
VFB2
Adjustable output, V+ = 4.5V to 28V, SKIP = VCC TON = GND (620kHz) V+ = 15V, VOUT1 = 1.5V TON = REF (485kHz) TON = open (345kHz) TON = VCC (235kHz) TON = GND (460kHz) V+ = 15V, VOUT2 = 1.5V TON = REF (355kHz) TON = open (255kHz) TON = VCC (170kHz)
DH1 On-Time (Note 3)
tON1
DH2 On-Time (Note 3)
tON2
On-Time Tracking Minimum Off-Time MAX1540A LDO Output-Voltage Accuracy tOFF(MIN) LINEAR REGULATOR (LDO) (Note 1) VLDOOUT
tON2 with respect to tON1 (Note 3) (Note 3) ON1 = ON2 = GND, V+ = 6V to 28V
V
8
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Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = -40C to +85C, unless otherwise noted.) (Note 4)
PARAMETER MAX1541 LDO Output-Voltage Accuracy (Fixed VLDOOUT) SYMBOL VLDOOUT CONDITIONS FBLDO = ON1 = ON2 = GND, VLDOIN = 6V to 28V FBLDO = LDOOUT, ON1 = ON2 = GND, VLDOIN = 4.5V to 28V 0 < ILDOOUT < 10mA 0 < ILDOOUT < 100mA 0 < ILDOOUT < 10mA 0 < ILDOOUT < 100mA MIN 4.85 4.65 1.212 1.175 MAX 5.10 V 5.10 1.275 V 1.275 800 800 mV UNITS
MAX1540A/MAX1541
MAX1541 LDO Feedback Accuracy (Adjustable VLDOOUT)
VFBLDO
MAX1540A: V+ - VLDOOUT, ILDOOUT = 50mA Dropout Voltage REFERENCE (REF) Reference Voltage REFIN1 Input Bias Current FAULT DETECTION Overvoltage Trip Threshold Output Undervoltage-Protection Trip Threshold PGOOD_ Lower Trip Threshold PGOOD_ Upper Trip Threshold PGOOD_ Output Low Voltage VCC Undervoltage-Lockout Threshold CURRENT LIMIT Current-Limit Input Range Valley Current-Limit Threshold (Fixed) Valley Current-Limit Threshold (Adjustable) INPUTS AND OUTPUTS Logic Input Threshold LDOON Input Trip Level Dual Mode Threshold Voltage ON1, ON2, SKIP, GATE, rising edge, hysteresis = 225mV Rising edge, hysteresis = 250mV FB1 (MAX1540A), FB2 (MAX1540A/MAX1541) High Low 1.2 1.2 1.9 0.05 CSP_ CSN_ VLIM_ (VAL) VCSP_ - VCSN_, ILIM_ = VCC VLIM_ (VAL) VCSP_ - VCSN_, VILIM_ = 2.00V 0 -0.3 40 160 VUVLO(VCC) With respect to error-comparator threshold, OVP/UVP = VCC With respect to error-comparator threshold, OVP/UVP = VCC With respect to error-comparator threshold, hysteresis = 1% With respect to error-comparator threshold, hysteresis = 1% ISINK = 4mA Rising edge, PWM disabled below this level, hysteresis = 20mV 4.1 10 64 -14 +5 VREF IREFIN1 VCC = 4.5V to 5.5V, IREF = 0 1.98 MAX1541: VLDOIN - VLDOOUT, ILDOOUT = 50mA
2.02 0.05
V A
21 76 -5 +14 0.3 4.4
% % % % V V
2.7 +28.0 60 240
V
mV mV
2.2 1.3 2.1 0.15
V V V
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9
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = -40C to +85C, unless otherwise noted.) (Note 4)
PARAMETER SYMBOL CONDITIONS High Four-Level Input Logic Levels TON, OVP/UVP, LSAT, SKIP, FBLANK Open REF Low MIN VCC 0.4V 3.15 1.65 3.85 2.35 0.5 V MAX UNITS
Note 1: For the MAX1540A, the gate-driver input supply (VDD) is internally connected to the fixed 5V linear-regulator output (LDOOUT), and the linear-regulator input supply (LDOIN) is internally connected to the battery voltage input (V+). Note 2: When the inductor is in continuous conduction, the output voltage has a DC regulation level higher than the error-comparator threshold by 50% of the ripple. In discontinuous conduction (SKIP = GND, light load), the output voltage has a DC regulation level higher than the trip level by approximately 1.5% due to slope compensation. Note 3: On-time and off-time specifications are measured from 50% point to 50% point at the DH_ pin with LX_ = GND, VBST_ = 5V, and a 250pF capacitor connected from DH_ to LX_. Actual in-circuit times may differ due to MOSFET switching speeds. Note 4: Specifications to -40C are guaranteed by design, not production tested.
Typical Operating Characteristics
(MAX1541 circuit of Figure 12, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TON = REF, TA = +25C, unless otherwise noted.)
OUT2 EFFICIENCY vs. LOAD CURRENT (VOUT2 = 2.5V)
MAX1540A toc01
2.5V OUTPUT VOLTAGE (OUT2) vs. LOAD CURRENT
MAX1540A toc02
OUT1 EFFICIENCY vs. LOAD CURRENT (VOUT1 = 1.0V)
95 90 EFFICIENCY (%) 85 80 75 70 65 60 VIN = 7V VIN = 12V VIN = 20V 0.01 0.1 1 10 SKIP = GND SKIP = VCC
MAX1540A toc03
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 0.01 0.1 1 VIN = 7V VIN = 12V VIN = 20V SKIP = GND SKIP = VCC
2.55 2.54 OUTPUT VOLTAGE (V) 2.53 2.52 2.51 2.50 2.49 2.48 SKIP = GND SKIP = VCC 0 1 2 3 4 5
100
55 50
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
10
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
Typical Operating Characteristics (continued)
(MAX1541 circuit of Figure 12, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TON = REF, TA = +25C, unless otherwise noted.)
1.0V OUTPUT VOLTAGE (OUT1) vs. LOAD CURRENT
MAX1540A toc04
MAX1540A/MAX1541
OUT2 SWITCHING FREQUENCY vs. LOAD CURRENT (VOUT2 = 2.5V)
MAX1540A toc05
OUT1 SWITCHING FREQUENCY vs. LOAD CURRENT (VOUT1 = 1.0V)
MAX1540A toc06
1.02 SKIP = GND SKIP = VCC OUTPUT VOLTAGE (V) 1.01
600 500 400 300 200 100 SKIP = GND SKIP = VCC 0 1 2 3 4 5
600 500 400 300 200 100 0 0 1 2 3 4 5
1.00
0.99
SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
SKIP = GND SKIP = VCC
0.98 0 1 2 3 4 5 LOAD CURRENT (A)
0 LOAD CURRENT (A)
LOAD CURRENT (A)
SWITCHING FREQUENCY vs. INPUT VOLTAGE
MAX1540A toc07
MAXIMUM OUTPUT CURRENT vs. INPUT VOLTAGE
5.8 MAXIMUM OUTPUT CURRENT (A) 5.6 5.4 5.2 5.0 4.8 4.6 4.4 4.2 2.5V OUTPUT
MAX1540A toc08
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (FORCED-PWM OPERATION)
MAX1540A toc09
450 2.5V OUTPUT SKIP = VCC SWITCHING FREQUENCY (kHz) 400 4A LOAD 350 NO LOAD 300
6.0
20
16 SUPPLY CURRENT (mA) IBIAS 12 IIN 8
250
4 SKIP = ON1 = ON2 = VCC 0 0 4 8 12 16 20 24 28 0 4 8 12 16 20 24 28 INPUT VOLTAGE (V) INPUT VOLTAGE (V)
200 0 4 8 12 16 20 24 28 INPUT VOLTAGE (V)
4.0
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (PULSE-SKIPPING OPERATION)
MAX1540Atoc10
2.0V REFERENCE LOAD REGULATION
MAX1540A toc11
REFERENCE DISTRIBUTION
SAMPLE SIZE = 50 SAMPLE PERCENTAGE (%) 40
MAX1540A toc12
1.00 IBIAS SUPPLY CURRENT (mA)
4 REFERENCE VOLTAGE DEVIATION (mV) 3 2 1 0 -1 -2 -3 -4
50
30
0.10
20
IN SKIP = GND ON1 = ON2 = VCC 0.01 0 4 8 12 16 20 24 28 INPUT VOLTAGE (V)
10
-20
0
20
40
60
80
100
0 1.990
1.995
2.000
2.005
2.010
REFERENCE LOAD CURRENT (A)
REFERENCE VOLTAGE (V)
______________________________________________________________________________________
11
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Typical Operating Characteristics (continued)
(MAX1541 circuit of Figure 12, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TON = REF, TA = +25C, unless otherwise noted.)
LINEAR-REGULATOR OUTPUT (LDOOUT) vs. LOAD CURRENT
MAX1540A toc13
STARTUP WAVEFORM (HEAVY LOAD)
MAX1540A toc14
3.36 3.34 LDO OUTPUT VOLTAGE (V) 3.32 3.30 3.28 3.26 3.24 VLDOIN = 12V VLDOIN = 5V
3.3V 0 4A 2A 0 2.5V
A
B
C 0 D 400s/div A. ON2, 5V/div B. INDUCTOR CURRENT, 2A/div 0.5 LOAD C. OUT2, 2V/div D. PGOOD2, 5V/div
3.22 3.20 0 20 40 60 80 100 LDO LOAD CURRENT (mA) 0
STARTUP WAVEFORM (LIGHT LOAD)
MAX1540A toc15
SHUTDOWN WAVEFORM (DISCHARGE MODE DISABLED)
MAX1540A toc16
3.3V 0 4A 2A 0 2.5V
A
3.3V 0 2.5V
A
B B 0 0 5V D C 0 5V D 200s/div A. ON2, 5V/div B. INDUCTOR CURRENT, 2A/div 100 LOAD 100 LOAD, OVP/UVP = REF OR GND C. OUT2, 2V/div D. PGOOD2, 5V/div E 0 10ms/div A. ON2, 5V/div B. OUT2, 2V/div C. INDUCTOR CURRENT, 2A/div D. DL2, 5V/div E. PGOOD2, 5V/div C
0 0
12
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Typical Operating Characteristics (continued)
(MAX1541 circuit of Figure 12, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TON = REF, TA = +25C, unless otherwise noted.)
SHUTDOWN WAVEFORM (DISCHARGE MODE ENABLED)
MAX1540A toc17
2.5V OUTPUT LOAD TRANSIENT (FORCED PWM)
MAX1540A toc18
3.3V 0 2.5V
A
4A 0 2.6V 2.5V
A
B 0 0 5V D 0 5V E 0 1ms/div A. ON2, 5V/div B. OUT2, 2V/div C. INDUCTOR CURRENT, 2A/div D. DL2, 5V/div E. PGOOD2, 5V/div C
B
2.4V 4A C 0 12V D 0 40s/div A. IOUT2 = 0 TO 4A, 5A/div B. VOUT2 = 2.5V, 100mV/div SKIP = VCC C. INDUCTOR CURRENT, 5A/div D. LX2, 10V/div
100 LOAD, OVP/UVP = VCC OR OPEN
2.5V OUTPUT LOAD TRANSIENT (PULSE SKIPPING)
MAX1540A toc19
LINEAR-REGULATOR LOAD TRANSIENT
MAX1540A toc20
4A 0 2.6V 2.5V 2.4V 4A
A
100mA A
B
0 3.4V
C 0 12V D 0 40s/div A. IOUT2 = 0.1A TO 4A, 5A/div C. INDUCTOR CURRENT, 5A/div B. VOUT2 = 2.5V, 100mV/div D. LX2, 10V/div SKIP = GND 100s/div A. ILDOOUT = 1mA TO 100mA, 50mA/div B. VLDOOUT = 3.3V, 100mV/div SKIP = GND 3.3V 3.2V B
______________________________________________________________________________________
13
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Typical Operating Characteristics (continued)
(MAX1541 circuit of Figure 12, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TON = REF, TA = +25C, unless otherwise noted.)
LINEAR-REGULATOR LINE TRANSIENT
MAX1540A toc21
OUTPUT OVERLOAD (UVP DISABLED)
20A A 10A 0 B 5A 0 2.5V C C 0 5V 0 D 40s/div B
MAX1540A toc22
20V 10V 20V 10V 3.8V 3.3V 2.8V 200s/div A. INPUT (VIN), 10V/div B. LDOIN (10V TO 20V), 10V/div 20mA LOAD
A
C. LDOOUT (3.3V), 500mV/div
A. LOAD (0 TO 150m), 10A/div C. 2.5V OUTPUT, 2V/div B. INDUCTOR CURRENT, 10A/div D. PGOOD2, 5V/div OVP/UVP = OPEN OR GND
OUTPUT OVERLOAD (UVP ENABLED)
20A 10A 0 5A 0 5V 0 2.5V D 5V 0 20s/div A. LOAD (0 TO 150m), 10A/div D. 2.5V OUTPUT, 2V/div B. INDUCTOR CURRENT, 10A/div E. PGOOD2, 5V/div C. DL2, 5V/div OVP/UVP = VCC OR REF E 0 7.5A
MAX1540A toc23
INDUCTOR-SATURATION PROTECTION (LSAT DISABLED)
MAX1540A toc24
5A A 0 2.5V 0.67V
A
B C
B C
D
20s/div A. IOUT2 = 0 TO 5A, 5A/div B. 2.5V OUTPUT, 200mV/div LSAT = GND, L = 3.3H 3.5A C. ILIM, 100mV/div D. INDUCTOR CURRENT, 5A/div
14
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Typical Operating Characteristics (continued)
(MAX1541 circuit of Figure 12, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TON = REF, TA = +25C, unless otherwise noted.)
INDUCTOR-SATURATION PROTECTION (VILIM = 200mV)
5A 0 2.5V 0.67V 0.47V 7.5A 0 20s/div A. IOUT2 = 0 TO 5A, 5A/div B. 2.5V OUTPUT, 200mV/div LSAT = REF, L = 3.3H 3.5A
MAX1540A toc25
INDUCTOR-SATURATION PROTECTION (VILIM = 400mV)
A 5A 0 B C 2.5V 1.5V 5V 0.67V D 0.27V 5A 0 20s/div A. IOUT2 = 0 TO 5A, 5A/div B. 2.5V OUTPUT, 1V/div C. PGOOD, 5V/div LSAT = REF, L = 3.3H 3.5A
MAX1540A toc26
A
B C D E
C. ILIM, 200mV/div D. INDUCTOR CURRENT, 5A/div
D. ILIM, 400mV/div E. INDUCTOR CURRENT, 5A/div
MAX1541 DYNAMIC OUTPUT-VOLTAGE TRANSITION (CREFIN1 = 100pF)
MAX1540A toc27
MAX1541 DYNAMIC OUTPUT-VOLTAGE TRANSITION (CREFIN1 = 1nF)
MAX1540A toc28
5V 0 1.5V 1.5V 1V 5V 5A 0
A
5V A 0 1.5V 1.5V
B C D E
B C D E
1V 5V 5A 0 -5A
-5A 40s/div A. GATE, 5V/div D. PGOOD1, 5V/div B. OUT1 (1.0V TO 1.5V), 0.5V/div E. INDUCTOR CURRENT, 5A/div C. REFIN1, 0.5V/div 200mA LOAD, SKIP = GND
100s/div A. GATE, 5V/div D. PGOOD1, 5V/div B. OUT1 (1.0V TO 1.5V), 0.5V/div E. INDUCTOR CURRENT, 5A/div C. REFIN1, 0.5V/div 200mA LOAD, SKIP = GND
______________________________________________________________________________________
15
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Pin Description
PIN MAX1540A MAX1541 NAME FUNCTION Overvoltage/Undervoltage Protection and Discharge-Mode Control Input. This fourlevel logic input selects between various output fault-protection options (Table 7) by selectively enabling OVP protection and UVP protection. When enabled, the OVP limit defaults at 116% of the nominal output voltage, and the UVP limit defaults at 70% of the nominal output voltage. Discharge mode is enabled when OVP protection is also enabled. Connect OVP/UVP to the following pins for the desired function: VCC = enable OVP and discharge mode, enable UVP. Open = enable OVP and discharge mode, disable UVP. REF = disable OVP and discharge mode, enable UVP. GND = disable OVP and discharge mode, disable UVP. See the Fault Protection and (ON_) sections. Pulse-Skipping Control Input. This four-level logic input enables or disables the lightload pulse-skipping operation of each output: VCC = OUT1 and OUT2 in forced-PWM mode. Open = OUT1 in forced-PWM mode, OUT2 in pulse-skipping mode. REF = OUT1 in pulse-skipping mode, OUT2 in forced-PWM mode. GND = OUT1 and OUT2 in pulse-skipping mode. Inductor-Saturation Control Input. This four-level logic input sets the inductor-current saturation limit as a multiple of the valley current-limit threshold set by ILIM, or disables the function if not required. Connect LSAT to the following pins to set the saturation current limit: VCC = 2 x ILIM(VAL) Open = 1.75 x ILIM(VAL) REF = 1.5 x ILIM(VAL) GND = disable LSAT protection See the Inductor Saturation Limit and Setting the Current Limit sections. On-Time Selection Control Input. This four-level logic input sets the K-factor value used to determine the DH_ on-time (see the On-Time One-Shot (TON) section). Connect to analog ground (GND), REF, or VCC; or leave TON unconnected to select the following nominal switching frequencies: VCC = 235kHz (OUT1) / 170kHz (OUT2) Open = 345kHz (OUT1) / 255kHz (OUT2) REF = 485kHz (OUT1) / 355kHz (OUT2) GND = 620kHz (OUT1) / 460kHz (OUT2) Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through a series 20 resistor. Bypass VCC to analog ground with a 1F or greater ceramic capacitor. Buffered N-Channel MOSFET Gate Input. A logic low on GATE turns off the internal MOSFET so OD appears as high impedance. A logic high on GATE turns on the internal MOSFET, pulling OD to ground. Integrator Capacitor Connection for Controller 1. Connect a 47pF to 470pF (47pF typ) capacitor from CC1 to analog ground (GND) to set the integration time constant for the main MAX1541 controller (OUT1).
1
1
OVP/UVP
2
2
SKIP
3
3
LSAT
4
4
TON
5
5
VCC
--
6
GATE
--
7
CC1
16
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
Pin Description (continued)
PIN MAX1540A MAX1541 NAME FUNCTION Valley Current-Limit Threshold Adjustment for Controller 1. The valley current-limit threshold defaults to 50mV if ILIM1 is tied to VCC. In adjustable mode, the valley current-limit threshold across CSP1 and CSN1 is precisely 1/10 the voltage seen at ILIM1 over a 250mV to 2.5V range. The logic threshold for switchover to the 50mV default value is approximately VCC - 1V. When the inductor-saturation protection threshold is exceeded, ILIM1 sinks 6A. See the Current-Limit Protection section. Valley Current-Limit Threshold Adjustment for Controller 2. The valley current-limit threshold defaults to 50mV if ILIM2 is tied to VCC. In adjustable mode, the valley current-limit threshold across CSP2 and CSN2 is precisely 1/10th the voltage seen at ILIM2 over a 250mV to 2.5V range. The logic threshold for switchover to the 50mV default value is approximately VCC - 1V. When the inductor-saturation protection threshold is exceeded, ILIM2 sinks 6A. See the Current-Limit Protection section. 2.0V Reference Voltage Output. Bypass REF to analog ground with a 0.1F or greater ceramic capacitor. The reference can source up to 50A for external loads. Loading REF degrades output voltage accuracy according to the REF load-regulation error. The reference is disabled when the MAX1540A/MAX1541 are shut down. External Reference Input for Controller 1. REFIN1 sets the main feedback regulation voltage (VFB1 = VREFIN1) of the MAX1541. Open-Drain Output. Controlled by GATE. Positive Current-Sense Input for Controller 2. Connect to the positive terminal of the current-sense element. Figure 14 and Table 9 describe several current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ILIM2. Negative Current-Sense Input for Controller 2. Connect to the negative terminal of the current-sense element. Figure 14 and Table 9 describe several current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ILIM2. Feedback Input for Controller 2: MAX1540A: Connect to VCC for a +1.5V fixed output or to analog ground (GND) for a +2.5V fixed output. For an adjustable output (0.7V to 5.5V), connect FB2 to a resistive divider from OUT2. The FB2 regulation level is +0.7V. MAX1541: Connect to VCC for a +1.8V fixed output or to analog ground (GND) for a +2.5V fixed output. For an adjustable output (0.7V to 5.5V), connect FB2 to a resistive divider from OUT2. The FB2 regulation level is +0.7V. Output Voltage-Sense Connection for Controller 2. Connect directly to the positive terminal of the output capacitors as shown in the standard application circuits (Figures 1 and 12). OUT2 senses the output voltage to determine the on-time for the high-side switching MOSFET. OUT2 also serves as the feedback input when using the preset internal output voltages as shown in Figure 10. When discharge mode is enabled by OVP/UVP, the output capacitor is discharged through an internal 10 resistor connected between OUT2 and ground.
MAX1540A/MAX1541
6
8
ILIM1
7
9
ILIM2
8
10
REF
-- --
11 12
REFIN1 OD
9
13
CSP2
10
14
CSN2
11
15
FB2
12
16
OUT2
______________________________________________________________________________________
17
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Pin Description (continued)
PIN MAX1540A MAX1541 NAME FUNCTION Open-Drain Power-Good Output. PGOOD2 is low when the output voltage is more than 10% (typ) above or below the normal regulation point, during soft-start, and in shutdown. After the soft-start circuit has terminated, PGOOD2 becomes high impedance if the output is in regulation. High-Side Gate-Driver Output for Controller 2. DH2 swings from LX2 to BST2. Inductor Connection for Controller 2. Connect to the switched side of the inductor. LX2 serves as the lower supply rail for the DH2 high-side gate driver. Boost Flying-Capacitor Connection for Controller 2. Connect to an external capacitor and diode as shown in Figure 8. An optional resistor in series with BST2 allows the DH2 pullup current to be adjusted. Analog and Power Ground. Connect backside pad to GND. Low-Side Gate-Driver Output for Controller 2. DL2 swings from GND to LDOOUT (MAX1540A) or GND to VDD (MAX1541). Battery Voltage Input. The controller uses V+ to set the on-time one-shot timing. The DH on-time is inversely proportional to input voltage over a range of 2V to 28V. For the MAX1540A, V+ also serves as the linear-regulator input supply. Internal Linear-Regulator Input Supply. Power LDOIN from a 4.5V to 28V voltage source. Bypass LDOIN to GND with a 4.7F or greater capacitor. For the MAX1540A, LDOIN is internally connected to V+. For the MAX1541, LDOIN must be connected to VDD when LDO is not used. MAX1541 Supply Voltage Input for the DL_ Gate Driver. Connect to the system supply voltage (+4.5V to +5.5V). Bypass VDD to power ground with a 1F or greater ceramic capacitor. For the MAX1540A, LDOOUT supplies the DL_ gate drivers (VDD = LDOOUT). Linear Regulator Output. Bypass LDOOUT with a 1F or greater capacitor per 5mA of load (internal and external), with a minimum of 4.7F. For the MAX1540A, LDOOUT powers the DL_ gate drivers (VDD internally connected to LDOOUT). Feedback Input for the Linear Regulator. Connect to GND for a fixed 5V output. For an adjustable output (1.25V to VLDOIN - 0.6V), connect FBLDO to a resistive voltagedivider from LDOOUT to analog ground (GND). The FBLDO regulation voltage is +1.25V. For the MAX1540A, FBLDO is internally connected to GND for a fixed 5V output. Low-Side Gate-Driver Output for Controller 1. DL1 swings from GND to LDOOUT (MAX1540A) or GND to VDD (MAX1541). Linear-Regulator Enable Input. For automatic startup, connect to V+ or LDOIN (MAX1541). Connect to GND to shut down the linear regulator. Boost Flying-Capacitor Connection for Controller 1. Connect to an external capacitor and diode as shown in Figure 8. An optional resistor in series with BST1 allows the DH1 pullup current to be adjusted.
13
17
PGOOD2
14 15
18 19
DH2 LX2
16 17 18
20 21 22
BST2 GND DL2
19
23
V+
--
24
LDOIN
--
25
VDD
20
26
LDOOUT
--
27
FBLDO
21 22
28 29
DL1 LDOON
23
30
BST1
18
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
Pin Description (continued)
PIN MAX1540A 24 25 MAX1541 31 32 NAME LX1 DH1 FUNCTION Inductor Connection for Controller 1. Connect to the switched side of the inductor. LX1 serves as the lower supply rail for the DH1 high-side gate driver. High-Side Gate-Driver Output for Controller 1. DH1 swings from LX1 to BST1. Open-Drain Power-Good Output. PGOOD1 is low when the output voltage is more than 10% (typ) above or below the normal regulation point, during soft-start, and in shutdown. After the soft-start circuit has terminated, PGOOD1 becomes high impedance if the output is in regulation. For the MAX1541, PGOOD1 is blanked--forced high-impedance state--when FBLANK is enabled and the controller detects a transition on GATE. Output Voltage-Sense Connection for Controller 1. Connect directly to the positive terminal of the output capacitors as shown in the standard application circuits (Figures 1 and 12). OUT1 senses the output voltage to determine the on-time for the high-side switching MOSFET. For the MAX1540A, OUT1 also serves as the feedback input when using the preset internal output voltages as shown in Figure 10. When discharge mode is enabled by OVP/UVP, the output capacitor is discharged through it l 10 it t db t OUT1 d d Feedback Input for Controller 1: MAX1540A: Connect to VCC for a +1.2V fixed output or to analog ground (GND) for a +1.8V fixed output. For an adjustable output (0.7V to 5.5V), connect FB1 to a resistive divider from OUT1. The FB1 regulation level is +0.7V. MAX1541: The FB1 regulation level is set by the voltage at REFIN1. Negative Current-Sense Input for Controller 1. Connect to the negative terminal of the current-sense element. Figure 14 and Table 9 describe several current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ILIM1. Positive Current-Sense Input for Controller 1. Connect to the positive terminal of the current-sense element. Figure 14 and Table 9 describe several current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ILIM1. Fault-Blanking Control Input. This four-level logic input enables or disables fault blanking, and sets the forced-PWM operation time (tFBLANK). When fault blanking is enabled, PGOOD1 and the OVP/UVP protection for controller 1 are blanked for the selected time period after the MAX1541 detects a transition on GATE. Additionally, controller 1 enters forced-PWM mode for the duration of tFBLANK anytime GATE changes states. Connect FBLANK as follows: VCC = 220s tFBLANK, fault blanking enabled. Open = 140s tFBLANK, fault blanking enabled. REF = 65s tFBLANK, fault blanking enabled. GND = 140s tFBLANK, fault blanking disabled. See the Electrical Characteristics table for the tFBLANK limits.
MAX1540A/MAX1541
26
33
PGOOD1
27
34
OUT1
28
35
FB1
29
36
CSN1
30
37
CSP1
--
38
FBLANK
______________________________________________________________________________________
19
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Pin Description (continued)
PIN MAX1540A MAX1541 NAME FUNCTION OUT2 Enable Input. Pull ON2 to GND to shut down controller 2 (OUT2). Connect to VCC for normal operation. When discharge mode is enabled by OVP/UVP, the output is discharged through a 10 resistor between OUT2 and GND, and DL2 is forced high after VOUT2 drops below 0.3V. When discharge mode is disabled by OVP/UVP, OUT2 remains a high-impedance input and DL2 is forced low so LX2 also appears as a high impedance. A rising edge on ON1 or ON2 clears the fault-protection latch. OUT1 Enable Input. Pull ON1 to GND to shut down controller 1 (OUT1). Connect to VCC for normal operation. When discharge mode is enabled by OVP/UVP, the output is discharged through a 10 resistor between OUT1 and GND, and DL1 is forced high after VOUT1 drops below 0.3V. When discharge mode is disabled by OVP/UVP, OUT1 remains a high-impedance input and DL1 is forced low so LX1 also appears as high impedance. A rising edge on ON1 or ON2 clears the fault-protection latch. Exposed Backside Pad. Connect the exposed backside pad to analog ground.
31
39
ON2
32
40
ON1
--
--
EP
Table 1. Component Selection for Standard Applications
COMPONENT Input Voltage (VIN) Output Voltage (VOUT_) Load Current (IOUT_) Switching Frequency (fSW_) Input Capacitor (CIN) Output Capacitor (COUT_) High-Side MOSFET (NH_) Low-Side MOSFET (NL_) Low-Side Schottky (DL_) (if needed) MAX1540A PWM1 7V to 24V 1.8V 4A TON = REF (485kHz) PWM2 7V to 24V 2.5V 8A TON = REF (355kHz) PWM1 7V to 24V 1.0V/1.5V 4A TON = REF (485kHz) MAX1541 PWM2 7V to 24V 2.5V 4A TON = REF (355kHz)
(2) 10F, 25V Taiyo Yuden TMK432BJ106KM 220F, 6.3V, 12m Sanyo POSCAP 6TPD220M 35m, 30V Fairchild 1/2 FDS6982S 22m, 30V Fairchild 1/2 FDS6982S 1A, 30V Schottky Nihon EP10QS03L 2.5H, 6.2A, 15m Sumida CDEP105(H)-2R5 330F, 4V, 12m Sanyo POSCAP 4TPD330M 20m, 30V Fairchild FDS6690 12.5m, 30V Fairchild FDS6670S 1A, 30V Schottky Nihon EP10QS03L 2.2H, 10A, 4.4m Sumida CDEP105(L)-2R2
(2) 4.7F, 25V Taiyo Yuden TMK325BJ475KM 470F, 4V, 10m Sanyo POSCAP 4TPD470M 35m, 30V Fairchild 1/2 FDS6982S 22m, 30V Fairchild 1/2 FDS6982S 1A, 30V Schottky Nihon EP10QS03L 1.8H, 9.0A, 6.2m Sumida CDEP105(S)-1R8 220F, 6.3V, 12m Sanyo POSCAP 6TPD220M 35m, 30V Fairchild 1/2 FDS6982S 22m, 30V Fairchild 1/2 FDS6982S 1A, 30V Schottky Nihon EP10QS03L 4.3H, 6.8A, 8.7m Sumida CDEP105(L)-4R3
Inductor (L_)
RSENSE_
15m 1%, 0.5W 5m 1%, 0.5W 15m 1%, 0.5W 15m 1%, 0.5W IRC LR2010-01-R015F IRC LR2010-01-R005F IRC LR2010-01-R015F IRC LR2010-01-R015F or Dale WSL-2010-R015F or Dale WSL-2010-R005F or Dale WSL-2010-R015F or Dale WSL-2010-R015F
20
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
+5V BIAS SUPPLY C1 22F LDOOUT V+ INPUT (VIN)* 7V TO 20V CIN (2) 10F
DBST NH1 DH1 BST1 CBST1 0.1F LX1 DL1 L1 2.5H NL1 DL1
MAX1540A
DH2 BST2
DBST NH2
CBST2 0.1F LX2 DL2 GND CSP1 CSP2 RCS2 5m CSN1 CSN2 OUT2 FB2 OVP/UVP COUT2 330F OUTPUT 2 2.5V, 8A (MAX) NL2 DL2 L2 2.2H
RCS1 15m
OUTPUT 1 1.8V, 4A (MAX) COUT1 220F
OUT1 FB1 SKIP
REF CREF (485kHz/355kHz) 0.22F
LSAT TON REF LDOON ON1 ON2
OPEN (ILIM(VAL) x 1.75) ON
C3 470pF
R2 100k ILIM1 R3 49.9k
OFF R1 20 +5V BIAS SUPPLY
VCC C2 1F R6 100k R7 100k
C4 470pF
R4 200k ILIM2 R5 49.9k EP PGOOD1 PGOOD2
POWER-GOOD
POWER GROUND SEE TABLE 1 FOR COMPONENT SPECIFICATIONS. ANALOG GROUND *LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE.
Figure 1. MAX1540A Standard Application Circuit ______________________________________________________________________________________ 21
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Table 2. Component Suppliers
SUPPLIER Central Semiconductor Coilcraft Fairchild Semiconductor International Rectifier Kemet PHONE 631-435-1110 (USA) 800-322-2645 (USA) 888-522-5372 (USA) 310-322-3331 (USA) 408-986-0424 (USA) 65-6231-3226 (Singapore), 408-749-9714 (USA) 619-661-6835 (USA) 203-268-6261 (USA) 408-982-9660 (USA) 03-3667-3408 (Japan), 408-573-4150 (USA) 847-803-6100 (USA), 81-3-5201-7241 (Japan) 858-675-8013 (USA) WEBSITE www.centralsemi.com www.coilcraft.com www.fairchildsemi.com www.irf.com www.kemet.com
Detailed Description
The MAX1540A/MAX1541 provide three independent outputs with independent enable controls. They contain two Quick-PWM step-down controllers ideal for low-voltage power supplies for notebook computers, and a 100mA linear regulator. Maxim's proprietary Quick-PWM pulsewidth modulators in the MAX1540A/ MAX1541 are specifically designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The Quick-PWM architecture circumvents the poor load-transient timing problems of fixed-frequency currentmode PWMs, while also avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant-off-time PWM schemes. The MAX1540A linear regulator draws power from the battery voltage and generates a preset 5V, which can be used to bootstrap the buck controllers for automatic startup. The MAX1541's linear regulator can be connected to any input source from 4.5V to 28V to generate an adjustable output voltage as low as 1.25V, or as high as the input source with 800mV of dropout at 50mA load. Single-stage buck conversion allows the MAX1540A/ MAX1541 to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, twostage conversion (stepping down from another system supply rail instead of the battery at a higher switching frequency) allows the minimum possible physical size. The MAX1540A generates chipset, dynamic randomaccess memory (DRAM), CPU I/O, or other low-voltage supplies down to 0.7V. The MAX1541 powers chipsets and graphics processor cores that require dynamically adjustable output voltages, or generates the active termination bus that must track the input reference. The MAX1540A is available in a 32-pin thin QFN package with optional inductor-saturation protection and overvoltage/undervoltage protection. The MAX1541 is available in a 40-pin thin QFN package with optional inductor-saturation protection and overvoltage/undervoltage protection.
Panasonic
www.panasonic.com
Sanyo Siliconix (Vishay) Sumida
www.sanyovideo.com www.vishay.com www.sumida.com
Taiyo Yuden
www.t-yuden.com
TDK
www.component.tdk.com
TOKO
www.tokoam.com
Standard Application Circuits
The MAX1540A standard application circuit (Figure 1) generates a 1.8V and 2.5V rail for general-purpose use in a notebook computer. The MAX1541 Standard Application Circuit (Figure 12) generates a dynamically adjustable output voltage (OUT1), typical of a graphicsprocessor core requirement, and a fixed 2.5V output (OUT2). See Table 1 for component selections. Table 2 lists the component manufacturers.
+5V Bias Supply (VCC and VDD)
The MAX1540A/MAX1541 require a 5V bias supply in addition to the battery. This 5V bias supply is either the MAX1540A/MAX1541s' internal linear regulator or the notebook's 95%-efficient 5V system supply. Keeping the bias supply external to the IC can improve efficiency and allows the fixed 5V or adjustable linear regulator (MAX1541) to be used for other applications. For the MAX1540A, the gate-driver input supply (VDD) is con-
22
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Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
nected internally to the fixed 5V linear-regulator output (LDOOUT). The 5V bias supply must provide VCC (PWM controller) and VDD (gate-drive power), so the maximum current drawn is: IBIAS = ICC + fSW (QG(LOW) + QG(HIGH)) = 4mA to 50mA (typ) where ICC is 1.1mA (typ), fSW is the switching frequency, and Q G(LOW) and Q G(HIGH) are the MOSFET data sheet's total gate-charge specification limits at VGS = 5V. The V+ battery input and 5V bias inputs (VCC and VDD) can be connected together if the input source is a fixed 4.5V to 5.5V supply. If the 5V bias supply powers up prior to the battery supply, the enable signals (ON1 and ON2 going from low to high) must be delayed until the battery voltage is present in order to ensure startup. where K (switching period) is set by the TON pin-strap connection (Table 3). This algorithm results in a nearly constant switching frequency despite the lack of a fixedfrequency clock generator. The benefits of a constant switching frequency are twofold: 1) the frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band and 2) the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. The on-time for the main controller (DH1) is set 15% higher than the nominal frequency setting (200kHz, 300kHz, 420kHz, or 540kHz), while the on-time for the secondary controller (DH2) is set 15% lower than the nominal setting. This prevents audio-frequency "beating" between the two asynchronous regulators. The on-time one-shot has good accuracy at the operating points specified in the Electrical Characteristics (approximately 12.5% at 540kHz and 420kHz nominal settings, and 10% with the 300kHz and 200kHz settings). On-times at operating points far removed from the conditions specified in the Electrical Characteristics can vary over a wider range. The constant on-time translates only roughly to a constant switching frequency. The on-times guaranteed in the Electrical Characteristics are influenced by resistive losses and by switching delays in the high-side MOSFET. Resistive losses--including the inductor, both MOSFETs, and PC board copper losses in the output and ground-- tend to raise the switching frequency as the load increases. The dead-time effect increases the effective on-time, reducing the switching frequency as one or both dead times add to the effective on-time. It occurs only in PWM mode (SKIP = VCC) and during dynamic output-voltage transitions when the inductor current reverses at light- or negative-load currents. With reversed inductor current, the inductor's EMF causes LX_ to go high earlier than normal, extending the on-time by a period equal to the driver dead time. For loads above the critical conduction point, where the dead-time effect no longer occurs, the actual switching frequency is: fSW = t ON ( VIN + VDROP1 - VDROP2 ) VOUT_ + VDROP1
MAX1540A/MAX1541
Free-Running, Constant On-Time, PWM Controller with Input Feed Forward
The Quick-PWM control architecture is a pseudofixedfrequency, constant on-time, current-mode regulator with voltage feed forward (Figure 2). This architecture relies on the output filter capacitor's ESR to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The Quick-PWM algorithm is simple: the high-side switch on-time relies solely on an adjustable one-shot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. Another one-shot sets a fixed minimum off-time (400ns typ). The controller triggers the on-time one-shot when the error comparator is low, the inductor current is below the valley current-limit threshold, and the minimum off-time one-shot has timed out.
On-Time One-Shot (TON)
The heart of the PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to the battery and output voltages. The highside switch on-time is inversely proportional to the battery voltage as measured by the V+ input (VIN = V+), and proportional to the output voltage as measured by the OUT_ input: V On- Time = K OUT VIN
where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; VDROP2 is the sum of the resistances in the charging path, includ-
______________________________________________________________________________________
23
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
*V+ TON SKIP
MAX1540A/MAX1541
LSAT
ILIM1 CSP1 CSN1 CURRENT LIMIT 1 (FIGURE 5) CURRENT LIMIT 2 (FIGURE 5)
ILIM2 CSP2 CSN2
VALLEY CURRENT LIMIT BST1 DH1 LX1 *VDD DL1 GND **CC1
ZERO SATURATION CROSSING LIMIT
SATURATION LIMIT
ZERO CROSSING
VALLEY CURRENT LIMIT BST2 DH2
PWM CONTROLLER 1 (FIGURE 3) FAULT1 FAULT2
PWM CONTROLLER 2 (FIGURE 3)
LX2 *VDD DL2
INT FB1
INT REF1
INT FB2
INT REF2
GND
REF 2.0V REF **REFIN1 13R 7R VCC
INTERNAL MAX1540A/MAX1541 OPTION
0.7V
FB1 OUT1
FB1 DECODE (FIGURE 10)
FB2 DECODE (FIGURE 10)
FB2 OUT2
ON1 POWER-GOOD AND FAULT PROTECTION 1 (FIGURE 9) PGOOD1 POWER-GOOD AND FAULT PROTECTION 2 (FIGURE 9)
ON2
PGOOD2
**FBLANK **OD
QUAD-LEVEL DECODE AND TIMER
BLANK
ENABLE OVP ENABLE UVP
QUAD-LEVEL DECODE
OVP/UVP
*LDOIN **GATE MAX1541 CONTROLLER 1 ONLY LINEAR REGULATOR (FIGURE 13) *LDOOUT **FBLDO LDOON
*FOR THE MAX1540A: LDOIN IS CONNECTED TO V+. LDOOUT IS CONNECTED TO VDD. **MAX1541 CONTROLLER ONLY.
Figure 2. MAX1540A/MAX1541 Functional Diagram 24 ______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
Table 3. Approximate K-Factor Errors
CONTROLLER 1 (OUT1) NOMINAL TON SETTING (kHz) 200kHz (TON = VCC) 300kHz (TON = open) 420kHz (TON = REF) 540kHz (TON = GND) K-FACTOR ERROR (%) 10 10 12.5 12.5 TYPICAL K-FACTOR (s) 4.5 (235kHz) 3.0 (345kHz) 2.2 (485kHz) 1.7 (620kHz) MINIMUM VIN AT VOUT1 = 1.8V* (V) 2.28 2.52 2.91 3.42 CONTROLLER 2 (OUT2) TYPICAL K-FACTOR (s) 6.2 (170kHz) 4.1 (255kHz) 3.0 (355kHz) 2.3 (460kHz) MINIMUM VIN AT VOUT2 = 2.5V* (V) 2.96 3.18 3.48 3.87
MAX1540A/MAX1541
*See the Step-Down Converter Dropout Performance section (h = 1.5 and worst-case K-factor value used).
Table 4. SKIP Configuration Table
SKIP VCC Open REF GND OUT1 MODE Forced PWM Forced PWM Pulse skipping Pulse skipping OUT2 MODE Forced PWM Pulse skipping Forced PWM Pulse skipping
tinuous and discontinuous inductor-current operation (also known as the "critical-conduction" point). The load-current level at which PFM/PWM crossover occurs, ILOAD(SKIP), is equal to half the peak-to-peak ripple current, which is a function of the inductor value (Figure 4). This threshold is relatively constant, with only a minor dependence on battery voltage: K V - V V ILOAD(SKIP) OUT IN OUT 2L VIN where K is the on-time scale factor (Table 3). For example, in the MAX1541 Standard Application Circuit (Figure 12) (K = 3.0s, VOUT2 = 2.5V, VIN = 12V, and L = 4.3H), the pulse-skipping switchover occurs at: 2.5V x 3.0s 12V - 2.5V = 0.69A 2 x 4.3H 12V The crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels). DC-output accuracy specifications refer to the threshold of the error comparator. When the inductor is in continuous conduction, the MAX1540A/MAX1541 regulate the valley of the output ripple, so the actual DC output voltage is higher than the trip level by 50% of the output ripple voltage. In discontinuous conduction
25
ing the high-side switch, inductor, and PC board resistances; and t ON is the on-time calculated by the MAX1540A/MAX1541.
Light-Load Operation (SKIP)
The four-level SKIP input selects light-load, pulse-skipping operation by independently enabling or disabling the zero-crossing comparator for each controller (Table 4). When the zero-crossing comparator is enabled, the controller forces DL_ low when the current-sense inputs detect zero inductor current. This keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under light-load conditions to avoid overcharging the output. When the zero-crossing comparator is disabled, the controller maintains PWM operation under light-load conditions (see the ForcedPWM Mode section). Automatic Pulse-Skipping Mode In skip mode, an inherent automatic switchover to PFM takes place at light loads (Figure 3). This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The zero-crossing comparator differentially senses the inductor current across the current-sense inputs (CSP_ to CSN_). Once VCSP_ - VCSN_ drops below 5% of the current-limit threshold (2.5mV for the default 50mV current-limit threshold), the comparator forces DL_ low (Figure 3). This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between con-
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
*MAIN MAX1541 CONTROLLER (OUT1) ONLY CC1 CC1 R INT FB_ INT REF_ A Gm = 80 V 7R Q ERROR AMP tOFF(MIN) TRIG 1-SHOT SLOPE COMP
VALLEY CURRENT LIMIT
S Q R DH DRIVER
tON SATURATION LIMIT Q TRIG 1-SHOT DL DRIVER S V+ TON OUT_ Q ON-TIME COMPUTE R FAULT PROTECTION ZERO CROSSING
Figure 3. MAX1540A/MAX1541 PWM-Controller Functional Diagram
I = t INDUCTOR CURRENT
VIN - VOUT L
IPEAK
ILOAD = IPEAK/2
0
ON-TIME
TIME
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
(IOUT < ILOAD(SKIP)), the output voltage has a DC regulation level higher than the error-comparator threshold by approximately 1.5% due to slope compensation. Forced-PWM Mode The low-noise forced-PWM mode disables the zerocrossing comparator, which controls the low-side switch on-time. This forces the low-side gate-drive waveform to be constantly the complement of the highside gate-drive waveform, so the inductor current
26
reverses at light loads while DH_ maintains a duty factor of VOUT_ / VIN. The benefit of forced-PWM mode is to keep the switching frequency fairly constant. However, forced-PWM operation comes at a cost: the no-load 5V bias current remains between 4mA to 40mA, depending on the external MOSFETs and switching frequency. Forced-PWM mode is most useful for reducing audiofrequency noise, improving load-transient response, and providing sink-current capability for dynamic output-voltage adjustment. The MAX1541 uses forcedPWM operation during all dynamic output-voltage transitions (GATE transition detected) in order to ensure fast, accurate transitions. Since forced-PWM operation disables the zero-crossing comparator, the inductor current reverses under light loads, quickly discharging the output capacitors. FBLANK determines how long the MAX1541 maintains forced-PWM operation--typically 220s (FBLANK = VCC), 140s (FBLANK = open or GND), or 65s (FBLANK = REF).
Current-Limit Protection (ILIM_)
Valley Current Limit The current-limit circuit employs a unique "valley" current-sensing algorithm that uses a current-sense resistor between CSP_ and CSN_ as the current-sensing ele-
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
QUAD-LEVEL DECODE SATURATION LIMIT VCC - 1.0V LSAT
9R DH DRIVER R 6A 0.5V S VALLEY CURRENT LIMIT Q R
ILIM_
CSP_ ZERO CROSSING CSN_ SKIP
Figure 5. MAX1540A/MAX1541 Current-Limit Functional Diagram
ment (Figure 1). If the magnitude of the current-sense signal is above the valley current-limit threshold, the PWM controller is not allowed to initiate a new cycle (Figures 3 and 5). The actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the current-sense resistance, inductor value, and battery voltage. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. Figure 6 shows the valley current-limit threshold point. In forced-PWM mode, the MAX1540A/MAX1541 also implement a negative current limit to prevent excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit and tracks the positive current limit when ILIM is adjusted. The current-limit threshold is adjusted with an external resistor-divider at ILIM_. A 2A to 20A divider current is recommended for accuracy and noise immunity. The current-limit threshold adjustment range is from 25mV to 200mV. In the adjustable mode, the current-limit threshold voltage is precisely 1/10th the voltage seen at ILIM_. The threshold defaults to 50mV when ILIM_ is
IPEAK
ILOAD INDUCTOR CURRENT
ILIMIT
ILIM(VAL) = ILOAD(MAX) 1-
( LIR ) 2
0
TIME
Figure 6. Valley Current-Limit Threshold Point
connected to VCC. The logic threshold for switchover to the 50mV default value is approximately VCC - 1V. Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the differential current-sense signals seen by CSP_ and CSN_. Place the IC close to the sense resistor with short, direct traces, making a Kelvin-sense connection to the current-sense resistor.
______________________________________________________________________________________
27
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
Inductor-Saturation Limit The LSAT connection selects an upper current-sense limit as the inductor-saturation threshold, or disables the inductor-saturation protection feature altogether (LSAT = GND). When enabled, the inductor-saturation threshold is a multiple of the positive valley current-limit threshold (Table 5) and tracks the valley current limit when ILIM is adjusted. The selected inductor-saturation threshold should give sufficient headroom above the peak inductor current so switching noise does not accidentally trip the saturation protection. Selecting an excessively high threshold may allow inductor saturation to go undetected. For an inductor with a low LIR (the ratio of the inductor ripple current to the designed maximum load current) near 20%, select the lowest saturation threshold of 1.5 x ILIM(VAL) (LSAT = REF). When using an inductor with a higher LIR, increase the inductor-saturation threshold accordingly. When inductor-saturation protection is enabled, the MAX1540A/MAX1541 continuously monitor the inductor current through the voltage across the current-sense resistor. When the inductor-saturation threshold is exceeded, the MAX1540A/MAX1541 immediately turn off the high-side gate driver and enable a 6A discharge current on ILIM_ (Figure 7) at the beginning of the next DH_ on-time. This reduces the voltage on ILIM_ by VILIM where: RR VILIM = - A B IILIM(LSAT) RA +RB where the ILIM saturation fault sink current (IILIM(LSAT)) is typically 6A (see the Electrical Characteristics table). When using the default 50mV valley current-limit threshold (ILIM_ = VCC), the ILIM_ saturation fault sink current does not lower the current-limit threshold (Figure 5). If the inductor current remains below the saturation threshold during the next cycle, the controller disables the ILIM_ discharge current, allowing the ILIM_ voltage to return to its nominal set point. The inductor should not remain in saturation once the controller reduces the valley current limit. If the inductor remains saturated, the output voltage may drop low enough to trip the undervoltage fault protection (UVP enabled), causing the MAX1540A/MAX1541 to set the fault latch and shut down both outputs. Adding a capacitor from ILIM_ to GND slows the ILIM_ voltage change by the time constant = (RA || RB) x CILIM, where is between 5 to 10 switching periods. If the inductor saturation occurs only during a short load transient, the time constant allows the power supply to recover before the output voltage drops below the output undervoltage threshold. Set VILIM to be at least 30% of the ILIM_ set voltage. Calculate RA and RB using the equations below:
V VREF VILIM ILIM with set at 30% IILIM(LSAT) VILIM(SET) VILIM(SET) RB = RA V REF - 1 V ILIM(SET)
MAX1540A/MAX1541
RA =
MAX1540A MAX1541
REF RA TO VALLEY CURRENT-LIMIT COMPARATOR (FIGURE 2)
CREF
Inductor-saturation sensing works best when using a current-sense resistor in series with the inductor. See the Setting the Current Limit section for various current-sense configurations (Figure 14) and LSAT recommendations.
CILIM ILIM
Table 5. LSAT Configuration Table
RB
6A FROM LSAT COMPARATOR AND LOGIC (FIGURE 2)
LSAT VCC Open REF GND
INDUCTOR-SATURATION THRESHOLD 2.00 x ILIM(VAL) 1.75 x ILIM(VAL) 1.50 x ILIM(VAL) Disabled
Figure 7. Adjustable Current-Limit Threshold 28 ______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications where a large VIN - VOUT differential exists. An adaptive dead-time circuit monitors the DL_ output and prevents the high-side MOSFET from turning on until DL_ is off. A similar adaptive deadtime circuit monitors the DH_ output, preventing the lowside MOSFET from turning on until DH_ is off. There must be a low-resistance, low-inductance path from the DL_ and DH_ drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX1540A/MAX1541 interprets the MOSFET gates as "off" while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). The internal pulldown transistor that drives DL_ low is robust, with a 0.6 (typ) on-resistance. This helps prevent DL_ from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX_) quickly switches from ground to VIN. Applications with high input voltages and long inductive driver traces may require additional gateto-source capacitance to ensure fast-rising LX_ edges do not pull up the low-side MOSFETs gate, causing shoot-through currents. The capacitive coupling between LX_ and DL_ created by the MOSFET's gate-todrain capacitance (CRSS), gate-to-source capacitance (CISS-CRSS), and additional board parasitics should not exceed the following minimum threshold: C VGS(TH) > VIN RSS CISS Lot-to-lot variation of the threshold voltage can cause problems in marginal designs. Alternatively, adding a resistor less than 10 in series with BST_ can remedy the problem by increasing the turn-on time of the high-side MOSFET without degrading the turn-off time (Figure 8).
CBYP VDD (RBST)* CBST DH NH L DBST
MAX1540A/MAX1541
MAX1540A MAX1541
BST
INPUT (VIN)
LX VDD DL (CNL)* PGND NL
(RBST)* OPTIONAL--THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME. (CNL)* OPTIONAL--THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 8. Optional Gate-Driver Circuitry
Soft-start allows a gradual increase of the internal currentlimit level during startup to reduce the input surge currents. The MAX1540A/MAX1541 divide the soft-start period into five phases. During the first phase, the controller limits the current limit to only 20% of the full current limit. If the output does not reach regulation within 425s, soft-start enters the second phase, and the current limit is increased by another 20%. This process is repeated until the maximum current limit is reached after 1.7ms or when the output reaches the nominal regulation voltage, whichever occurs first (see the soft-start waveforms in the Typical Operating Characteristics).
Power-Good Output (PGOOD_)
PGOOD_ is the open-drain output for a window comparator that continuously monitors the output. PGOOD_ is actively held low in shutdown and during soft-start. After the digital soft-start terminates, PGOOD_ becomes high impedance as long as the respective output voltage is within 10% of the nominal regulation voltage set by FB_. When the output voltage drops 10% below or rises 10% above the nominal regulation voltage, the MAX1540A/MAX1541 pull the respective power-good output (PGOOD_) low by turning on the MOSFET (Figure 9). Any fault condition forces both PGOOD1 and PGOOD2 low until the fault latch is cleared by toggling
29
POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and soft-start counter, powering-up the reference, and preparing the PWM for operation. Until VCC reaches 4.25V (typ), VCC undervoltage lockout (UVLO) circuitry inhibits switching. The controller inhibits switching by pulling DH_ low, and holding DL_ low when OVP and shutdown discharge are disabled or forcing DL_ high when OVP and shutdown discharge are enabled (Table 7). When VCC rises above 4.25V and ON_ is driven high, the controller activates the PWM controller and initializes soft-start.
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Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Table 6. FBLANK Configuration Table
POWER-GOOD FAULT PROTECTION 0.9 x INT REF_ 1.1 x INT REF_ 0.7 x INT REF_ 1.16 x INT REF_ INT FB_
FBLANK VCC Open REF
ENABLE OVP ENABLE UVP *BLANK
OUT1 FAULT BLANKING Enabled Enabled Enabled Disabled
FORCED-PWM DURATION (MIN/TYP) (s) 120/220 80/140 35/65 80/140
GND
Shutdown and Output Discharge (ON_)
When the output discharge mode is enabled (OVP/UVP connected to V CC or left open), and either ON_ is pulled low or an OVP fault or thermal fault sets the fault latch (Table 7), the controller discharges each output through an internal 10 switch connected between OUT_ and ground. While the output discharges, DL_ is forced low and the PWM controller is disabled. Once the output voltage drops below 0.3V, the low-side driver pulls DL_ high, effectively clamping the output and LX_ switching node to ground. The reference remains active until both output voltages are below 0.3V to provide an accurate 0.3V discharge threshold. When OVP/UVP is connected to REF or GND, the controller does not actively discharge either output, and the DL_ driver remains low until the system reenables the controller. Under these conditions, the output discharge rate is determined by the load current and output capacitance. The controller detects and latches the discharge-mode state set by OVP/UVP on startup.
20ms TIMER
FAULT LATCH
FAULT POWERGOOD
POR
*MAIN MAX1541 CONTROLLER (OUT1) ONLY
Figure 9. Power-Good and Fault Protection
ON1 or ON2, or cycling VCC power below 1V. For logiclevel output voltages, connect an external pullup resistor between PGOOD_ and VCC. A 100k resistor works well in most applications. Note that the power-good window detectors are completely independent of the overvoltage and undervoltage-protection fault detectors.
Fault Blanking (MAX1541 FBLANK)
The main MAX1541 controller (OUT1) automatically enters forced-PWM operation during all dynamic outputvoltage transitions (GATE transition detected) in order to ensure fast, accurate transitions. FBLANK determines how long the main MAX1541 controller maintains forcedPWM operation (Table 6--typically 220s (FBLANK = V CC ), 140s (FBLANK = open or GND), or 65s (FBLANK = REF). When fault blanking is enabled (FBLANK = VCC, open, or REF), the MAX1541 also disables the overvoltage and undervoltage fault protection for OUT1, and forces PGOOD1 to a high-impedance state during the transition period selected by FBLANK (Table 6). This prevents fault protection from latching off the MAX1541 and the PGOOD1 signal from going low when the output voltage change (VOUT1) cannot occur as fast as the REFIN1 voltage change (VREFIN1).
30
Fault Protection
The MAX1540A/MAX1541 provide over/undervoltage fault protection (Figure 9). Drive OVP/UVP to enable and disable fault protection as shown in Table 7. Once activated, the controller continuously monitors the output for undervoltage and overvoltage fault conditions. Overvoltage Protection (OVP) When the output voltage rises above 116% of the nominal regulation voltage and OVP is enabled (OVP/UVP = VCC or open), the OVP circuit sets the fault latch, shuts down both the Quick-PWM controllers, immediately pulls DH1 and DH2 low, and forces DL1 and DL2 high. This turns on the synchronous-rectifier MOSFETs with 100% duty, rapidly discharging the output capacitors and clamping both outputs to ground. Note that immediately latching DL_ high can cause the output voltages to go slightly negative due to energy stored in the output LC at the instant the OV fault occurs. If the load
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Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reversepolarity clamp. If the condition that caused the overvoltage persists (such as a shorted high-side MOSFET), the input fuse blows. The MAX1541 ignores OVP faults on OUT1 when it detects a transition on GATE (FBLANK enabled). Toggle ON1 or ON2, or cycle VCC power below 1V to clear the fault latch and restart the controller. OVP is disabled when OVP/UVP is connected to REF or GND (Table 7). Undervoltage Protection (UVP) When the output voltage drops below 70% of the nominal regulation voltage and UVP is enabled (OVP/UVP = VCC or REF), the controller sets the fault latch and activates the output discharge sequence (see the Shutdown and Output Discharge (ON_) section) of both outputs. When the output voltage drops to 0.3V, the driver pulls DL high so the synchronous rectifier turns on, clamping the output to GND. UVP is ignored for at least 10ms (min) after startup (ON_ rising edge), and when transitions are detected on GATE (MAX1541 only, FBLANK enabled). Toggle ON1 or ON2, or cycle VCC power below 1V to clear the fault latch and restart the controller. UVP is disabled when OVP/UVP is left open or connected to GND (Table 7). Thermal Fault Protection The MAX1540A/MAX1541 feature a thermal fault-protection circuit. When the linear regulator is disabled (LDOON = GND), the controller sets the thermal limit at +160C. When the linear regulator is enabled (LDOON = VCC), the controller sets the thermal limit at +150C to protect the internal linear regulator from continuous short-circuit conditions. Once the junction temperature exceeds the thermal limit, the thermal-protection circuit activates the fault latch, pulls PGOOD1 and PGOOD2 low, disables the linear regulator, and activates the output discharge sequence of both outputs regardless of the OVP/UVP setting. Toggle ON1 or ON2, or cycle VCC power below 1V to reactivate the controller after the junction temperature cools by 10C.
MAX1540A/MAX1541
Output Voltage
Preset Output Voltages The MAX1540A/MAX1541s' Dual Mode operation allows the selection of common voltages without requiring external components (Figure 10). For the main controller (OUT1) of the MAX1540A, connect FB1 to GND for a fixed 1.8V output, to VCC for a fixed 1.2V output, or connect FB1 directly to OUT1 for a fixed 0.7V output. For the secondary controller (OUT2) of the MAX1540A, connect FB2 to GND for a fixed 2.5V output, to VCC for a fixed 1.5V output, or connect FB2 directly to OUT2 for a fixed 0.7V output. The main controller (OUT1) of the MAX1541 regulates to the voltage set at REFIN1 (VFB1 = VREFIN1) and does not support Dual Mode operation. For the secondary controller (OUT2) of the MAX1541, connect FB2 to GND for a fixed 2.5V output, to VCC for a fixed 1.8V output, or connect FB2 directly to OUT2 for a fixed 0.7V output. Table 8 shows the output voltage configuration.
Table 7. Fault Protection and Shutdown Setting Truth Table
OVP/UVP ON_ DISCHARGE* Yes. Output discharged through a 10 resistor, and DL forced high when output drops below 0.3V. Yes. Output discharged through a 10 resistor, and DL forced high when output drops below 0.3V. No. DL forced low when shut down. No. DL forced low when shut down. UVP PROTECTION OVP PROTECTION THERMAL PROTECTION
VCC
Yes. UVP fault activates Yes. DH pulled low and DL the discharge sequence. forced high immediately.
Yes. Thermal fault activates the discharge sequence.
Open
No. UVP disabled.
Yes. DH pulled low and DL forced high immediately.
Yes. Thermal fault activates the discharge sequence. Yes. Thermal fault activates the discharge sequence. Yes. Thermal fault activates the discharge sequence.
REF
Yes. UVP fault activates No. OVP disabled. the discharge sequence. No. UVP disabled. No. OVP disabled.
GND
*Discharge-mode state latched on power-up. ______________________________________________________________________________________ 31
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
MAX1540A/MAX1541
TO ERROR AMPLIFIER FB_ FIXED OUTPUT FB = VCC OUT_
REF (2.0V)
FIXED OUTPUT FB = GND
9R
R
Figure 10. MAX1540A/MAX1541 Dual Mode Feedback Decoder
Table 8. Output Voltage Configuration
OUT1 OUT2 MAX1540A MAX1541 MAX1540A MAX1541 FB_ = VCC FB_ = GND FB_ = OUT_ or adjustable Fixed 1.2V Fixed 1.8V 0.7V Not allowed Not allowed VREFIN1 Fixed 1.5V Fixed 2.5V 0.7V Fixed 1.8V Fixed 2.5V 0.7V
Setting VOUT with a Resistive Voltage-Divider at FB_ The output voltage can be adjusted from 0.7V to 5.5V using a resistive voltage-divider (Figure 11). The MAX1540A regulates FB1 and FB2 to a fixed 0.7V reference voltage. The MAX1541 regulates FB1 to the voltage set at REFIN1 and regulates FB2 to a fixed 0.7V reference voltage. This makes the main MAX1541 controller (OUT1) ideal for memory applications where the termination supply must track the supply voltage. The adjusted output voltage is: R VOUT_ = VFB_ 1+ C RD where V FB_ = 0.7V for the MAX1540A, and V FB1 = VREFIN1 and VFB2 = 0.7V for the MAX1541.
32
Dynamic Output Voltages (MAX1541 OUT1 Only) The MAX1541 regulates FB1 to the voltage set at REFIN1. By changing the voltage at REFIN1, the MAX1541 can be used in applications that require dynamic output-voltage changes between two set points. Figure 12 shows a dynamically adjustable resistive voltage-divider network at REFIN1. Using the GATE signal and open-drain output (OD), a resistor can be switched in and out of the REFIN1 resistor-divider, changing the voltage at REFIN1. A logic high on GATE turns on the internal N-channel MOSFET, forcing OD to a low-impedance state. A logic low on GATE disables the N-channel MOSFET, so OD is high impedance. The two output voltages (FB1 = OUT1) are determined by the following equations: R9 VOUT1(LOW) = VREF R8+R9 (R9+R10) VOUT1(HIGH) = VREF R8+(R9+R10) The main MAX1541 controller (OUT1) automatically enters forced-PWM operation on the rising and falling edges of GATE, and remains in forced-PWM mode for a minimum time selected by FBLANK (Table 6). ForcedPWM operation is required to ensure fast, accurate negative voltage transitions when REFIN1 is lowered. Since forced-PWM operation disables the zero-crossing comparator, the inductor current may reverse under
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Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
L LX_ RSENSE COUT DL_ GND NL
MAX1540A/MAX1541
voltage during dynamic transitions. With the additional capacitance, the REFIN1 voltage slews between the two set points with a time constant given by R EQ x CREFIN1, where REQ is the equivalent parallel resistance seen by the slew capacitor. Looking at Figure 12, the time constant for a positive REFIN1 voltage transition is: R8 x (R9+R10) POS = CREFIN1 R8+(R9+R10) and the time constant for a negative REFIN1 voltage transition is:
MAX1540A/MAX1541
CSP_ CSN_ OUT_ FB_ RC
R8 x R9 NEG = C R8+R9 REFIN1
Linear Regulator (LDO)
RD
Figure 11. Setting VOUT with a Resistive Voltage-Divider at FB_
light loads, quickly discharging the output capacitors. If fault blanking is enabled, the MAX1541 also disables the main controller's (OUT1) overvoltage and undervoltage fault protection, and forces PGOOD1 to a highimpedance state for the period selected by FBLANK (Table 6). For a step-voltage change at REFIN1, the rate of change of the output voltage is limited by the inductor current ramp, the total output capacitance, the current limit, and the load during the transition. The inductor current ramp is limited by the voltage across the inductor and the inductance. The total output capacitance determines how much current is needed to change the output voltage. Additional load current slows down the output-voltage change during a positive REFIN1 voltage change, and speeds up the output-voltage change during a negative REFIN1 voltage change. For fast positive output-voltage transitions, the current limit must be greater than the load current plus the transition current: d ILIMIT > ILOAD + COUT V dt Adding a capacitor across REFIN1 and GND filters noise and controls the rate of change of the REFIN1
The maximum input voltage for the linear regulator is 28V, while the minimum input voltage is determined by the 800mV (max) dropout voltage (V LDOIN(MIN) = VLDOOUT + VDROPOUT) at 50mA load. Bypass the linear regulator's output (LDOOUT) with a 4.7F or greater capacitor, providing at least 1F per 5mA of internal and external load on the linear regulator. The LDO can source up to 100mA for powering the controller or supplying a small external load. For the MAX1540A, the linear regulator provides the 5V bias supply that powers the gate drivers and analog controller (Figure 1), providing stand-alone capability. The linear regulator's input is internally connected to the battery voltage input (LDOIN = V+), and the gatedriver input supply is internally connected to the linear regulator's output (VDD = LDOOUT). Figure 13 is the internal linear-regulator functional diagram. For the MAX1541, the linear regulator supports Dual Mode operation to allow the selection of a 5V output voltage without requiring external components (Figure 1). Connect FBLDO to GND for a fixed 5.0V output. The linear regulator's output voltage can be adjusted from 1.25V to 5.5V using a resistive voltage-divider (Figure 12). The MAX1541 regulates FBLDO to a 1.25V feedback voltage. The adjusted output voltage is: R11 VLDOOUT = VFBLDO 1+ R12 where VFBLDO = 1.25V. If unused, disable the MAX1541 linear regulator by connecting LDOON to GND.
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33
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
+5V BIAS SUPPLY INPUT (VIN)* 7V TO 20V CIN (2) 4.7F
C1 1F VDD V+
DBST NH1 DH1 BST1 CBST1 0.1F LX1 DL1 L1 1.8H NL1 DL1 SKIP CSP1 RCS1 15m OUTPUT 1 VOUT(HIGH) = 1.5V VOUT(LOW) = 1.0V CSN1 OUT1 COUT1 470F FB1 CCC1 47pF CC1 CREF 0.22F REF CILIM1 470pF R2 100k ILIM1 R3 49.9k CILIM2 470pF R4 100k ILIM2 R5 49.9k
MAX1541
DH2 BST2
DBST NH2
CBST 0.1F LX2 DL2 GND CSP2 RCS2 15m CSN2 OUT2 FB2 OVP/UVP COUT2 220F OUTPUT 2 VOUT2 = 2.5V NL2 DL2 L2 4.3H
R9 VOUT(LOW) = VREF (R8 + R9 ) VOUT(HIGH) = VREF
(
)
(R9 + R10) [R8 + (R9 + R10)]
LSAT TON LDOON ON1 ON2
OPEN (ILIM(VAL) x 1.75) REF (485kHz/355kHz) ON
OFF R1 20 +5V BIAS SUPPLY
VCC C2 1F R6 100k R7 100k
PGOOD1 VOUT(LOW) GATE VOUT(HIGH) OPEN (ENABLED, 140s) REF R8 75k R9 75k OD CREFIN 470pF EP R10 150k R12 20k LDOIN FBLANK REFIN1 LDOOUT R11 32.4k FBLDO C4 22F C3 4.7F PGOOD2 R13 10
POWER-GOOD
+5V BIAS SUPPLY
LDO OUTPUT VLDOOUT = 3.3V
POWER GROUND SEE TABLE 1 FOR COMPONENT SPECIFICATIONS. ANALOG GROUND *LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE.
Figure 12. MAX1541 Standard Application Circuit 34 ______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
V+ *LDOIN INTERNAL LDOIN OPTION BETWEEN THE MAX1540A/MAX1541 LDOOUT INTERNAL VDD OPTION BETWEEN THE MAX1540A/MAX1541 *VDD FIXED 5V
VL REG AND REF LDOON
GATE DRIVER AND ERROR AMP
*FBDLO
INTERNAL FBLDO OPTION BETWEEN THE MAX1540A/MAX1541
0.2V *MAX1541 ONLY.
Figure 13. Internal Linear-Regulator Functional Diagram
Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: * Input voltage range: The maximum value (VIN(MAX)) must accommodate the worst-case, high AC-adapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. * Maximum load current: There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components.
*
Switching frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. Inductor operating point: This choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output ripple due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further sizereduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. When pulse skipping (SKIP low and light loads), the inductor value also determines the load-current value at which PFM/PWM switchover occurs.
35
*
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Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Inductor Selection
The switching frequency and inductor operating point determine the inductor value as follows: L= VIN x fSW x ILOAD(MAX) x LIR VOUT (VIN - VOUT )
Setting the Current Limit
The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the ripple current; therefore: VOUT (VIN(MIN) - VOUT ) ILIM(VAL) > ILOAD(MAX) - 2VIN(MIN) fSW L where ILIM(VAL) equals the minimum valley current-limit threshold voltage divided by the current-sense resistance (RSENSE). For the 50mV default setting, the minimum valley current-limit threshold is 40mV. Connect ILIM_ to VCC for a default 50mV valley currentlimit threshold. In adjustable mode, the valley currentlimit threshold is precisely 1/10th the voltage seen at ILIM_. For an adjustable threshold, connect a resistive divider from REF to analog ground (GND) with ILIM_ connected to the center tap. The external 250mV to 2V adjustment range corresponds to a 25mV to 200mV valley current-limit threshold. When adjusting the current limit, use 1% tolerance resistors and a divider current of approximately 10A to prevent significant inaccuracy in the valley current-limit tolerance. The current-sense method (Figure 14) and magnitude determine the achievable current-limit accuracy and power loss (Table 9). Typically, higher current-sense voltage limits provide tighter accuracy, but also dissipate more power. Most applications employ a valley current-sense voltage (VLIM(VAL)) of 50mV to 100mV, so the sense resistor may be determined by: RSENSE = VLIM(VAL) / ILIM(VAL) For the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in Figure 14a. This configuration constantly monitors the inductor current, allowing accurate valley current-limiting and inductor-saturation protection. For low-output-voltage applications that require higher efficiency, the current-sense resistor can be connected between the source of the low-side MOSFET (NL_) and power ground (Figure 14b) with CSN_ connected to the drain of NL_ and CSP_ connected to power ground. In this configuration, the additional current-sense resistance only dissipates power when NL_ is conducting current. Inductor-saturation protection must be disabled with this configuration (LSAT = GND) since the inductor current is only properly sensed when the lowside MOSFET is turned on.
For example: ILOAD(MAX) = 4A, VIN = 12V, VOUT2 = 2.5V, fSW = 355kHz, 30% ripple current or LIR = 0.3: L= 2.5V x (12V - 2.5V) = 4.65H 12V x 355kHz x 4 A x 0.3
Find a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): LIR IPEAK = ILOAD(MAX) 1 + 2 Most inductor manufacturers provide inductors in standard values, such as 1.0H, 1.5H, 2.2H, 3.3H, etc. Also look for nonstandard values, which can provide a better compromise in LIR across the input voltage range. If using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values.
Transient Response
The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the ontime and minimum off-time:
V xK L(ILOAD(MAX) )2 OUT + t OFF(MIN) VIN VSAG = ( VIN - VOUT ) x K 2COUT x VOUT - t OFF(MIN) VIN
where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics) and K is from Table 3. The amount of overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as: VSOAR
36
(ILOAD(MAX) )2L
2COUT x VOUT
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Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
For high-power applications that do not require highaccuracy current sensing or inductor-saturation protection, the MAX1540A/MAX1541 can use the low-side MOSFET's on-resistance as the current-sense element (RSENSE = RDS(ON)) by connecting CSN_ to the drain of NL_ and CSP_ to the source of NL_ (Figure 14c). Use the worst-case maximum value for RDS(ON) from the MOSFET data sheet, and add some margin for the rise in RDS(ON) with temperature. A good general rule is to allow 0.5% additional resistance for each C of temperature rise. Inductor-saturation protection must be disabled with this configuration (LSAT = GND) since the inductor current is only properly sensed when the lowside MOSFET is turned on. Alternatively, high-power applications that require inductor saturation can constantly detect the inductor current by connecting a series RC circuit across the inductor (Figure 14d) with an equivalent time constant: L = CEQ x REQ RL where RL is the inductor's series DC resistance. In this configuration, the current-sense resistance is equivalent to the inductor's DC resistance (RSENSE = RL). Use the worst-case inductance and RL values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. In all cases, ensure an acceptable valley current-limit threshold voltage and inductor-saturation configurations despite inaccuracies in sense-resistance values. For processor-core voltage converters and other applications where the output is subject to violent load transients, the output capacitor's size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: RESR VSTEP ILOAD(MAX)
MAX1540A/MAX1541
In applications without large and fast load transients, the output capacitor's size often depends on how much ESR is needed to maintain an acceptable level of output voltage ripple. The output ripple voltage of a stepdown controller equals the total inductor ripple current multiplied by the output capacitor's ESR. Therefore, the maximum ESR required to meet ripple specifications is: VRIPPLE RESR ILOAD(MAX) x LIR The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONs, polymers, and other electrolytics). When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). However, lowcapacity filter capacitors typically have high-ESR zeros that may affect the overall stability (see the OutputCapacitor Stability Considerations section).
Output Capacitor Selection
The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements.
Table 9. Current-Sense Configurations
METHOD a) Output current-sense resistor CURRENT-SENSE ACCURACY High INDUCTOR-SATURATION PROTECTION Allowed (highest accuracy) Not allowed (LSAT = GND) Not allowed (LSAT = GND) Allowed CURRENT-SENSE POWER LOSS (EFFICIENCY) RSENSE x IOUT2
VOUT 2 1- V x RSENSE x IOUT IN
b) Low-side current-sense resistor
High
c) Low-side MOSFET on-resistance d) Equivalent inductor DC resistance
Low Low
No additional loss No additional loss
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37
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
VIN DH LX CIN L RSENSE VOUT COUT
MAX1540A DL MAX1541
GND CONNECT TO PREFERRED LSAT SETTING CSP LSAT CSN
a) OUTPUT SERIES RESISTOR SENSING DH LX CIN
VIN
L VOUT COUT
MAX1540A DL MAX1541
CSN RSENSE
DISABLE LSAT
CSP LSAT GND
b) LOW-SIDE SERIES RESISTOR SENSING
VIN DH LX CSN COUT CIN L VOUT
MAX1540A DL MAX1541
DISABLE LSAT CSP LSAT GND DH LX CIN
VIN INDUCTOR L RL VOUT COUT REQ CEQ
c) LOW-SIDE MOSFET SENSING
MAX1540A DL MAX1541
GND
CONNECT TO PREFERRED LSAT SETTING
CSP LSAT CSN RBIAS = REQ
d) LOSSLESS INDUCTOR SENSING
Figure 14. Current-Sense Configurations
38
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Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
Output-Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: f fESR SW where: fESR = 1 2RESR COUT
Input-Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents:
MAX1540A/MAX1541
IRMS =
X=1 VIN
2
I2OUTX VOUTX (VIN - VOUTX)
For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum and OS-CON capacitors in widespread use at the time of publication have typical ESR zero frequencies of 25kHz. In the design example used for inductor selection, the ESR needed to support 25mVP-P ripple is 25mV/1.2A = 20.8m. One 220F/4V Sanyo polymer (TPE) capacitor provides 15m (max) ESR. This results in a zero at 48kHz, well within the bounds of stability. Do not put high-value ceramic capacitors directly across the feedback sense point without taking precautions to ensure stability. Large ceramic capacitors can have a high-ESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. Unstable operation manifests itself in two related but distinctly different ways: double pulsing and fast-feedback loop instability. Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This "fools" the error comparator into triggering a new cycle immediately after the 400ns minimum offtime period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to monitor simultaneously the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot.
For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. If the MAX1540A/MAX1541 are operated as the second stage of a two-stage power conversion system, tantalum input capacitors are acceptable. In either configuration, choose a capacitor that has less than 10C temperature rise at the RMS input current for optimal reliability and lifetime.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN) should be roughly equal to the losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher, consider increasing the size of NH. Conversely, if the losses at VIN(MAX) are significantly higher, consider reducing the size of NH. If VIN does not vary over a wide range, maximum efficiency is achieved by selecting a high-side MOSFET (NH) that has conduction losses equal to the switching losses. Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., 8-pin SO, DPAK, or D2PAK), and is reasonably priced. Ensure that the MAX1540A/MAX1541 DL_ gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drain-to-gate capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems may occur. Switching losses are not an issue for the low-side MOSFET since it is a zero-voltage switched device when used in the step-down topology.
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39
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Power-MOSFET Dissipation
Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at minimum input voltage: V PD (NH Resistance) = OUT (ILOAD )2 x RDS(ON) VIN Generally, use a small high-side MOSFET to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often restricts how small the MOSFET can be. The optimum occurs when the switching losses equal the conduction (R DS(ON) ) losses. High-side switching losses do not become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: PD (NH The absolute worst case for MOSFET power dissipation occurs under heavy overload conditions that are greater than ILOAD(MAX) but are not high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, "overdesign" the circuit to tolerate: V (V - VOUT ) ILOAD = IVALLEY(MAX) + OUT IN 2VIN fSW L where I VALLEY(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and sense-resistance variation. The MOSFETs must have a relatively large heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward-voltage drop low enough to prevent the low-side MOSFET's body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 the load current. This diode is optional and can be removed if efficiency is not critical.
Applications Information
Step-Down Converter Dropout Performance
The output-voltage adjustable range for continuousconduction operation is restricted by the nonadjustable minimum off-time one-shot. For best dropout performance, use the slower (200kHz) on-time setting. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. This error is greater at higher frequencies (Table 3). Also, keep in mind that transient-response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (IDOWN) as much as it ramps up during the on-time (IUP). The ratio h = IUP/IDOWN indicates the controller's ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and V SAG greatly increases unless additional output capacitance is used.
(VIN(MAX) )2 CRSS x fSW x ILOAD Switching) =
IGATE
where CRSS is the reverse transfer capacitance of NH, and IGATE is the peak gate-drive source/sink current (1A typ). Switching losses in the high-side MOSFET can become a heat problem when maximum AC adapter voltages are applied due to the squared term in the switchingloss equation (C VIN2 fSW). If the high-side MOSFET chosen for adequate R DS(ON) at low-battery voltages becomes extraordinarily hot when subjected to VIN(MAX), consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum battery voltage:
V PD (NL Resistance) = 1- OUT (ILOAD )2 x RDS(ON) VIN(MAX)
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______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
A reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: VIN(MIN) = VOUT + VDROP1 h x t OFF(MIN) 1- K put voltages, it can produce three or more output voltages if required by using discrete logic or a DAC. Figure 15 shows an application circuit providing four voltage levels using discrete logic. Switching resistors in and out of the resistor network changes the voltage at REFIN1. An edge-detection circuit is added to generate a 1s pulse on GATE to trigger the fault blanking and forced-PWM operation. When using PWM mode (SKIP = VCC or open) on the main controller, the edgedetection circuit is only required if fault blanking is enabled. Otherwise, leave OD unconnected.
MAX1540A/MAX1541
where V DROP1 is the parasitic voltage drop in the charge path (see the On-Time One-Shot (TON) section), tOFF(MIN) is from the Electrical Characteristics, and K is taken from Table 3. The absolute minimum input voltage is calculated with h = 1. If the calculated VIN(MIN) is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate VSAG to be sure of adequate transient response. Dropout Design Example * * * * * * VOUT2 = 2.5V fSW = 355kHz K = 3.0s, worst-case KMIN = 3.3s tOFF(MIN) = 500ns VDROP1 = 100mV h = 1.5 VIN(MIN) = 2.5V + 0.1V = 3.47V 1.5 x 500ns 1- 3.0s
Active Bus Termination (MAX1541 OUT1 Only)
Active-bus-termination power supplies generate a voltage rail that tracks a set reference. They are required to source and sink current. DDR memory architecture requires active bus termination. In DDR memory architecture, the termination voltage is set at exactly half the memory supply voltage. Configure the main MAX1541 controller (OUT1) to generate the termination voltage using a resistive voltage-divider at REFIN1. In such an application, the main MAX1541 controller (OUT1) must be kept in PWM mode (SKIP = VCC or open) in order for it to source and sink current. Figure 16 shows the main MAX1541 controller configured as a DDR termination regulator. Connect GATE and FBLANK to GND when unused.
REF R4 R1 REFIN1 R3 A GND R2
B
Calculating again with h = 1 and the typical K-factor value (K = 3.3s) gives the absolute limit of dropout: VIN(MIN) = 2.5V + 0.1V = 3.06V 1 x 500ns 1- 3.3s
C1
MAX1541
Therefore, VIN must be greater than 3.06V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 3.47V.
1.5k
1000pF GATE
Multi-Output Voltage Settings (MAX1541 OUT1 Only)
While the main MAX1541 controller (OUT1) is optimized to work with applications that require two dynamic out-
1.5k
1000pF
Figure 15. Multi-Output Voltage Settings ______________________________________________________________________________________ 41
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
VDDQ VCC SKIP 10k LX1 REFIN1 10nF 10k DL1 COUT DH1 VIN CIN L RSENSE V VTT = DDQ 2
MAX1541 GND
CSP1 OD GATE FBLANK CSN1 OUT1 FB1 VDDQ = DDR MEMORY SUPPLY VOLTAGE VTT = TERMINATION SUPPLY VOLTAGE
Figure 16. Active Bus Termination
Voltage Positioning
In applications where fast load transients occur, the output voltage changes instantly by ESRCOUT x ILOAD. Voltage positioning allows the use of fewer output capacitors for such applications, and maximizes the output voltage AC and DC tolerance window in tight-tolerance applications. Figure 17 shows the connection of OUT_ and FB_ in voltage-positioned and nonvoltage-positioned circuits. In nonvoltage-positioned circuits, the MAX1540A/ MAX1541 regulate at the output capacitor. In voltagepositioned circuits, the MAX1540A/MAX1541 regulate on the inductor side of the current-sense resistor. VOUT_ is reduced to: VOUT(VPS) = VOUT(NO LOAD) - RSENSE x ILOAD Figure 18 shows the voltage-positioning transient response.
PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. * Minimize current-sensing errors by connecting CSP_ and CSN_ directly across the current-sense resistor (RSENSE_). When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. Route high-speed switching nodes (BST_, LX_, DH_, and DL_) away from sensitive analog areas (REF, FB_, CSP_, CSN_).
*
*
PC Board Layout Guidelines
Careful PC board layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 19). If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Follow these guidelines for good PC board layout: * Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. * Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing
Layout Procedure
1) Place the power components first, with ground terminals adjacent (NL _ source, CIN, COUT_, and DL _ anode). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the controller IC adjacent to the low-side MOSFET, preferably on the back side opposite NL _ and NH_ in order to keep LX_, GND, DH_, and the DL_ gate-drive lines short and wide. The DL_ and DH_ gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for proper adaptive dead-time sensing.
42
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
R1 +5V BIAS SUPPLY C2 VCC C1 V+ BST_ NH DH_ CBST L1 RSENSE VOLTAGE-POSITIONED OUTPUT (VOUT(VPS)) COUT CIN VDD DBST INPUT (VIN)
MAX1540A LX_ MAX1541
DL_ GND
NL
DL
CSP_ OUT_ FB CSN_
VOUT(VPS) = VOUT(NO LOAD) - RSENSEIOUT
Figure 17. Voltage Positioning
VOLTAGE POSITIONING THE OUTPUT
ESR VOLTAGE STEP (ISTEP x RESR) 1.4 A VOUT
CAPACITIVE SOAR (dV/dt = IOUT/COUT)
1.4 B CAPACITIVE SAG (dV/dt = IOUT/COUT) RECOVERY
50mV/div A. CONVENTIONAL CONVERTER B. VOLTAGE-POSITIONED OUTPUT
ILOAD
Figure 18. Voltage-Positioning Transient Response
______________________________________________________________________________________
43
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
VIA TO POWER GROUND
CONNECT THE EXPOSED PAD TO ANALOG GROUND VIA TO VCC BYPASS CAPACITOR MAX1540A TOP LAYER
CONNECT GND AND PGND TO THE CONTROLLER AT ONE POINT ONLY AS SHOWN VIA TO VCC PIN VIA TO REF BYPASS CAPACITOR VIA TO REF PIN MAX1540A BOTTOM LAYER
KELVIN-SENSE VIAS UNDER THE SENSE RESISTOR (REFER TO EVALUATION KIT)
DUAL N-CHANNEL MOSFET INDUCTOR
SINGLE N-CHANNEL MOSFETS
INDUCTOR DH LX DL COUT COUT CIN OUTPUT OUTPUT GROUND INPUT CIN
COUT GROUND
INPUT
HIGH-POWER LAYOUT
LOW-POWER LAYOUT
Figure 19. PC Board Layout
3) Group the gate-drive components (BST_ diode and capacitor, VDD bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as shown in Figures 1 and 12. This diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go, and an analog ground plane for sensitive analog components. The analog ground plane and power ground plane must meet only at a single point directly at the IC.
5) Connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the load as is practical.
Chip Information
TRANSISTOR COUNT: 8612 PROCESS: BiCMOS
44
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Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
Pin Configurations (continued)
LDOOUT LDOON FBLDO LDOIN BST1 V+
MAX1540A/MAX1541
TOP VIEW
30
29
28
27
26
25
24
23
22
21 20 19 18 17 16
GND
DL1
DL2
VDD
LX1 DH1 PGOOD1 OUT1 FB1
31 32 33 34 35 36 37 38 39 40 10
BST2 LX2 DH2 PGOOD2 OUT2
CSN1 CSP1
FBLANK
MAX1541
15 14 13 12 11
FB2 CSN2
CSP2
ON2 ON1
OD REFIN1
2
3
4
5
6
7
1
8 ILIM1
OVP/UVP
ILIM2
LSAT
SKIP
GATE
9
TON
THIN QFN
A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES.
______________________________________________________________________________________
CC1
VCC
REF
45
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
21-0140
K
1
2
46
______________________________________________________________________________________
QFN THIN.EPS
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX1540A/MAX1541
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
21-0140
K
2
2
______________________________________________________________________________________
47
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
48
______________________________________________________________________________________
QFN THIN.EPS
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX1540A/MAX1541
Revision History
Pages changed at Rev 3: 1, 10-15, 18, 20, 21, 22, 24, 34, 46-49
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 49 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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